Motorola M68000 User's Guide Page 218

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204 Assembly Language Programming for the 68000 Family
Figure 21 68030 Block diagram. (Courtesy of Motorola, Inc.)
Instruction and Data C aches
Figure 22 shows the organization of the 68030 data cache. The cache
consists of 16 entries. Each entry contains four longwords. A valid bit
is provided for each of these four longwords. If the valid bit is set, it
indicates that the data in the cache entry is valid for access. A reference
to this longword by a program would then obtain it from the cache rather
than from the physical memory. The organization of the instruction cache
is identical. These cache organizations differ slightly from the 68020. The
68020 instruction cache consists of 64 longword entries. This yields a cache
of the same size, but with a different organization. Studies that Motorola
performed have indicated that the organization used with the 68030 has
a better performance.
A problem exists with a data cache that doesn’t exist with an instruc
tion cache. Since an assumption is made that the instructions of a program
can never be modified by the program itself, the information contained
in the instruction cache never has to be written back to memory. No
such assumption can be made about data. In fact, a program that didnt
modify any memory locations containing data would be highly unlikely.
Since the stack can contain data, the memory occupied by the stack falls
into this category. If we allow the data contained in the data cache to be
modified, we must take steps to assure that the actual memory location
is modified as well.
A number of techniques exist to make sure that cache contents and
memory contents are updated correcdy. One method is to modify only
the contents of the cache when a write operation is issued. As long as the
entry remains in the cache, subsequent reads will have the correct results.
If an entry is replaced in the cache, the updated data can be written to
physical memory at that time. An alternate approach is to update the
contents of physical memory as soon as a write is issued. This means that
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