Motorola M68000 User's Guide Page 217

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CHAPTER 15
THE 68030
In the latter part of 1986 Motorola announced its latest member of
the 68000 family, the MC68030. This new super chip should be in full
production during 1987. This second-generation 32-bit microprocessor is
actually a combination of an enhanced MC68020 and a subset of the
MC68851 paged memory management unit. The combination really gives
awesome capability to one single tiny chip.
Programming the 68030 will be no different from programming the
68020 unless you are involved with the PMMU (paged memory manage
ment unit) portion of the chip. In that case, you would need to know the
details of the MC68851 coprocessor subset. I will not present all these
details; rather, I will give an introduction to the concepts of memory
management so that you can read the manufacturers documentation on
the 68030 or 68851 with less difficulty. At the time of this writing only
preliminary documentation on the 68030 was available. The information
presented here is as accurate as possible with this preliminary documen
tation.
The 68030 operates at 20 MHz, compared to a top speed of 16.7 MHz
for the 68020. However, the 68030 actually has an effective speed which
is twice that of the 68020. This is accomplished by a combination of
data and instruction caches and a pipelined architecture. You will recall
from Chapter 14 that the 68020 has an instruction cache. Its purpose is
to reduce the access time to instructions in memory. It is most effective
for program loops that are small enough to be entirely contained in the
cache. The operation of the instruction cache in the 68030 is similar to
that of the instruction cache in the 68020. However, the addition of a data
cache allows a greater improvement in speed. Both the instruction cache
and the data cache are 256 bytes. Figure 21 shows the block diagram of
the 68030. You will notice that there are two internal address and data
buses. This duplication allows simultaneous access to the instruction and
data caches.
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