Motorola M68000 User's Guide download pdf (Page 220)

206 Assembly Language Programming for the 68000 Family

Pipelined Architecture

Pipelining is a technique used on high performance CPU’s such as

mainframes. With pipelining, the CPU can execute operations for sev

eral instructions in parallel. Instructions are fed into a prefetch queue or

pipe. The 68030 contains an instruction pipe capable of holding three

16-bit values. These three words can represent from one to three com

plete instructions. The 68030 has three independent arithmetic logic units

(ALU’s). These are used to calculate instruction addresses and operand

addresses, and to perform data operations. In combination with the in

struction pipe, these three ALU’s allow concurrent operations to be per

formed. Arithmetic operations are not always performed concurrently,

but when possible they are. The CPU does this automatically, with the

end result of a faster overall operating speed. The more concurrency the

better. The fact that the instruction and data caches allow additional con

currency adds to this effective speed even more.

Paged Memory Management

As Figure 21 showed, the PMMU is added in between the internal

address buses and the external address bus. If the PMMU is not activated

on the 68030, the physical addressing is identical to the 68020. The

address bus is a 32-bit bus. This allows direct access to 4 gigabytes

of physical memory. This is truly an enormous amount of memory by

today’s megabyte standards. However, consider that a 68030 processor

might support many users simultaneously, that we might actually have

substantially less than the maximum permitted memory, and that this

memory would have to be divided up among these users. The more users,

the less actual physical memory is available to each user. The only way to

allow a user to seemingly occupy more memory than is actually available

is to implement a virtual memory, briefly discussed in Chapter 13. It

is possible to implement a virtual memory with either the 68010 or the

68020. However, they would both require external hardware. The PMMU

of the 68030 gives us a built-in capability for a virtual memory.

The 68030 PMMU implements a rather sophisticated version of pag

ing. Before we discuss the specifics of the 68030, let’s take a look at how

a basic paging mechanism works. Paging divides the virtual or logical

address space into equal size blocks called pages (Chapter 13). We

do the same for the physical memory. Each page in the logical address

space is mapped to a corresponding page frame in the physical address

space. Each byte in the page corresponds to the same byte in the phys

ical page frame. This requires that pages and page frames be the same

size. It is customary for the page size to be a power of 2. This makes it

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Motorola M68000 User's Guide Page 220