Motorola MVME2400 Series Service Manual Page 73

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Functional Description
http://www.mcg.mot.com/literature 2-15
2
The selection of either internal or external PPC arbitration mode is made
by sampling an RD line at the release of reset. Please see the section titled
“PHB Hardware Configuration” in this chapter for more information.
PHB has been designed to accommodate up to four PPC60x bus masters,
including itself (HAWK), two processors (CPU0/CPU1) and an external
PPC60x master (EXTL). EXTL can be an L2 cache, a second bridge chip,
etc. When the PPC Arbiter is disabled, PHB will generate an external
request and listen for an external grant for itself. It will also listen to the
other external grants to determine the PPC60x master identification field
(XID) within the GCSR. When the PPC Arbiter is enabled, PHB will
receive requests and issue grants for itself and for the other three bus
masters. The XID field will be determined by the PPC Arbiter.
The PPC60x arbitration signals and their functions are summarized in
Table 2-6.
While RST_ is asserted, XARB0 through XARB4 will be held in tri-state.
If the internal arbiter mode is selected, then XARB0 through XARB3 will
be driven to an active state no more than ten clock periods after PHB has
detected a rising edge on RST_. If the external arbiter mode has been
selected, then XARB4 will be driven to an active state no more than ten
clock periods after PHB has detected a rising edge on RST_.
The PPC Arbiter implements the following prioritization scheme:
Table 2-6.PPC Arbiter Pin Assignments
Pin Name
Pin
Type
Reset
Internal Arbiter External Arbiter
Direction Function Direction Function
XARB0 BiDir Tristate Output CPU0 Grant_ Input CPU0 Grant_
XARB1 BiDir Tristate Output CPU1 Grant_ Input CPU1 Grant_
XARB2 BiDir Tristate Output EXTL Grant_ Input EXTL Grant_
XARB3 BiDir Tristate Input CPU0 Request_ Output HAWK Request_
XARB4 Input - - Input CPU1 Request_ Input HAWK Grant_
XARB5 Input - - Input EXTL Request_ Input - -
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