Motorola MVME2400 Series Service Manual Page 180

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2-122 Computer Group Literature Center Web Site
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
2
MASK MASK. Setting this bit disables any further interrupts
from this source. If the mask bit is cleared while the bit
associated with this interrupt is set in the IPR, the interrupt
request will be generated.
ACT ACTIVITY. The activity bit indicates that an interrupt
has been requested or that it is in-service. The ACT bit is
set to a one when its associated bit in the Interrupt Pending
Register or In-Service Register is set.
POL POLARITY. This bit sets the polarity for external
interrupts. Setting this bit to a zero enables active low or
negative edge. Setting this bit to a one enables active high
or positive edge. Only External Interrupt Source 0 uses
this bit in this register.
SENSE SENSE. This bit sets the sense for external interrupts.
Setting this bit to a zero enables edge sensitive interrupts.
Setting this bit to a one enables level sensitive interrupts.
For external interrupt sources 1 through 15, setting this bit
to a zero enables positive edge triggered interrupts.
Setting this bit to a one enables active low level triggered
interrupts.
PRIOR PRIORITY. Interrupt priority 0 is the lowest and 15 is
the highest. Note that a priority level of 0 will not enable
interrupts.
VECTOR VECTOR. This vector is returned when the Interrupt
Acknowledge register is examined upon acknowledgment
of the interrupt associated with this vector.
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