Motorola MVME2400 Series Service Manual download pdf (Page 257)

Programming Model

http://www.mcg.mot.com/literature 3-71

tdp tdp determines the minimum number of clock cycles that the

SMC assumes the SDRAM requires to satisfy its Tdp parameter.

When tdp

is 0, the minimum time provided for Tdp is 1 clock.

When tdp

is 1, the minimum is 2 clocks.

trp

trp determines the minimum number of clock cycles that the

SMC assumes the SDRAM requires to satisfy its Trp parameter.

When trp

is 0, the minimum time provided for Trp is 2 clocks.

When trp

is 1 the minimum is 3 clocks.

trcd

trcd determines the minimum number of clock cycles that the

SMC assumes the SDRAM requires to satisfy its Trcd

parameter. When trcd

is 0, the minimum time provided for Trcd

is 2 clocks. When trcd

is 1 the minimum is 3 clocks.

Address Parity Error Log Register

apelog

apelog is set when a parity error occurs on the PPC60x address

bus during any PPC60x address cycle (TS_ asserted to AACK_

asserted). It is cleared by writing a one to it or by power-up reset.

ape_tt0-4 ape_tt is the value that was on the TT0-TT4 signals when the

apelog

bit was set.

ape_ap0-3 APE_AP is the value that was on the AP0-AP7 signals when the

apelog

bit was set.

ape_me

When ape_me is set, the transition of the apelog bit from false

to true causes the Hawk to pulse its machine check interrupt

request pin (MCHK0_) true. When ape_me

is cleared, apelog

does not affect the MCHK0_ pin.

ADDRESS

$FEF800E0

BIT

NAME

apelog

ape_tt0

ape_tt1

ape_tt2

ape_tt3

ape_tt4

ape_ap0

ape_ap1

ape_ap2

ape_ap3

ape_me

OPERATION

R/C

R/W

READ ZERO

RESET

0 P

0 PL

1 2 ... 252 253 254 255 256 257 258 259 260 261 262 ... 353 354

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Motorola MVME2400 Series Service Manual Page 257

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