Motorola MVME2400 Series Service Manual download pdf (Page 105)

Functional Description

http://www.mcg.mot.com/literature 2-47

All PCI Configuration cycles intended for internal PHB registers will also

be delayed if PHB is busy so that control bits which may affect write

posting do not change until all write posted transactions have completed.

For the same reason all PPC60x write posted transfers will also be

completed before any access to the PHB PPC registers is begun.

The PCI Local Bus Specification 2.1 states that posted write buffers in

both directions must be flushed before completing a read in either

direction. PHB supports this by providing two optional FIFO flushing

options. The XFBR (PPC60x Flush Before Read) bit within the GCSR

PPC-originated read transactions. The PFBR (PCI Flush Before Read) bit

within the GCSR register controls the flushing of PPC write posted data

when performing PCI-originated read transactions. The PFBR and XFBR

functions are completely independent of each other, however both

functions must be enabled to guarantee full compliance with PCI Local

Bus Specification 2.1.

When the XFBR bit is set, the PHB will handle read transactions

originating from the PPC bus in the following manner:

❏ Write posted transactions originating from the processor bus are

flushed by the nature of the FIFO architecture. The PHB will hold

the processor with wait states until the PCI bound FIFO is empty.

❏ Write posted transactions originated from the PCI bus are flushed

whenever the PCI slave has accepted a write-posted transaction and

the transaction has not completed on the PPC bus.

The PPC Slave address decode logic settles out several clocks after the

assertion of TS_, at which time the PPC Slave can determine the

transaction type. If it is a read and XFBR is enabled, the PPC Slave will

look at the ‘ps_fbrabt’ signal. If this signal is active, the PPC Slave will

retry the processor.

When the PFBR bit is set, PHB will handle read transactions originating

from the PCI bus in the following manner:

❏ Write posted transactions originating from the PCI bus are flushed

by the nature of the FIFO architecture. The PHB will hold the PCI

Master with wait states until the PPC bound FIFO is empty.

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Motorola MVME2400 Series Service Manual Page 105