Registers
http://www.mcg.mot.com/literature 2-71
2
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PPC Arbiter/PCI Arbiter Control Registers
The PPC Arbiter Register
(XARB) provides control and status for the PPC
Arbiter. Please refer to the section titled PPC Arbiter for more
information. The bits within the XARB register are defined as follows:
FBRx Flatten Burst Read. This field is used by the PPC Arbiter
to control how bus pipelining will be affected after all
burst read cycles. The encoding of this field is shown in
the table below.
FSRx Flatten Single Read. This field is used by the PPC
Arbiter to control how bus pipelining will be affected after
all single beat read cycles. The encoding of this field is
shown in the table below.
FBWx Flastten Burst Write. This field is used by the PPC
Arbiter to control how bus pipelining will be affected after
all burst write cycles. The encoding of this field is shown
in the table below.
MID Current PPC Data Bus Master
00 device on ABG0*
01 device on ABG1*
10 device on ABG2
11 Hawk
Address $FEFF000C
Bit
0123456789
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
Name XARB PARB
FBR1
FBR0
FSR1
FSR0
FBW1
FSW0
FSW1
FSW0
PRI
PRK1
PRK0
ENA
PRI1
PRI0
PRK3
PRK2
PRK1
PRK0
HIER2
HIER1
HIER0
POL
ENA
Operation RW
R
RW
RW
RW
R
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
Reset 0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
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