Motorola MVME2400 Series Service Manual download pdf (Page 70)

2-12 Computer Group Literature Center Web Site

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller

threshold should be lowered to anticipate any additional latencies incurred

by the PPC Master on the PPC60x bus. Table 2-3 summarizes the PHB

available write posting options.

The PPC Master has an optional read ahead mode controlled by the RAEN

bit in the PSATTx registers that allows the PPC Master to prefetch data in

bursts and store it in the PCI FIFO. The contents of the PCI FIFO will then

be used to satisfy the data requirements for the remainder of the PCI read

transaction. The PHB read ahead mechanism has been tuned for maximum

efficiency during typical operation conditions. If excessive latencies are

encountered on the PPC60x bus, it may be necessary to tune the read ahead

mechanism to compensate for this. Additional tuning of the read-ahead

function is controlled by the RXFT/RMFT (Read Any Fifo

Threshold/Read Multiple Fifo Threshold) fields in the PSATTx registers.

These fields can be used to characterize when the PPC Master will

continue reading ahead with respect to the PCI FIFO threshold. The FIFO

threshold should be raised to anticipate any additional latencies incurred

by the PPC Master on the PPC60x bus. Table 2-4 summarizes the PHB

available read ahead options.

Table 2-3. PPC Master Write Posting Options

WXFT WPEN PPC60x Start PPC60x Continuation

xx 0 FIFO = 1 dword FIFO = 1 dword

00 1 FIFO >= 4 cache lines FIFO >= 1 cache line

01 1 FIFO >= 3 cache lines FIFO >= 1 cache line

10 1 FIFO >= 2 cache lines FIFO >= 1 cache line

11 1 FIFO >= 1 cache lines FIFO >= 1 cache line

Table 2-4. PPC Master Read Ahead Options

RXFT RMFT RAEN PCI Command

Initial

Read Size

Continuation

Subsequent

Read Size

xx xx 0 Read 1 cache line PCI received

data and

FRAME_

asserted

1 cache line

Read Line

1 2 ... 65 66 67 68 69 70 71 72 73 74 75 ... 353 354

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Motorola MVME2400 Series Service Manual Page 70