B-88 MSC8101ADS RevB User’s Manual MOTOROLA
D5 CLK5 (PC27) I/O, T.S. Clock 5 input. When TDMB is enabled this pin is an input clock.
When TDMB port is disabled this line may be used for any
available function of PC27 Port C.
D6 ATMFCLK (PC26) I/O, T.S. ATM Transmit FIFO Clock. Upon the rising edge of this clock
(driven by the MSC8101), while the ATM port is enabled, the cell
octets are written to the PM5350’s transmit FIFO. This clock
samples ATMTXD(7:0), ATMTXPTY, ATMTXENb and ATMTSOC.
When the ATM port is disabled, this line may be used for any
available function of PC26.
D7 DACK2b(PC25) I/O, T.S. DMA channel 2 data acknowledge. Output from DMA port. Using
for external DMA tool. When the DMA port is disabled, this line
may be used for any available function of PC25.
D8 DREQ2b(PC24) I/O, T.S. DMA channel 2 data request acknowledge. This signal is
asserted by the DMA, indicating that the DMA has sampled the
peripheral request. Using for external DMA tool. When the DMA
port is disabled, this line may be used for any available function of
PC24.
D9 DACK1b(PC23) I/O, T.S. DMA channel 1 data acknowledge. Output from DMA port. Using
for external DMA tool. When the DMA port is disabled, this line
may be used for any available function of PC23.
D10 DREQ1b(PC22) I/O, T.S. DMA channel 1 data request acknowledge. This signal is
asserted by the DMA, indicating that the DMA has sampled the
peripheral request. Using for external DMA tool. When the DMA
port is disabled, this line may be used for any available function of
PC22.
D11 N.C. - Not connected.
D12
D13
D14
D15
D16
D17 PC15 I/O, T.S. MSC8101’s Port C15 Parallel I/O line. May be used to any of its
available functions.
D18 SCC1CDb (PC14) I/O, T.S. RS232 Port 1 Carrier Detect (L). Connected via RS232
transceiver to RS232 DTR1b input, allowing detection of a
connected terminal to this port. This line is simply a I/O input line
to the MSC8101.
When RS232 Port 1 is disabled, this line is tristated and may be
used for any available function of PC14.
D19 FETHMDC (PC13) I/O, T.S. Fast-Ethernet Port Management Data Clock. This slow clock (S/
W generated) qualifies the management data I/O to read / write
the LXT970’s internal registers.
When the Ethernet port is disabled, this line may be used for any
available function of PC13.
TABLE B1-3. P2 - CPM Expansion - Interconnect Signals
Pin No. Signal Name Attribute Description
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
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