36 MSC8101ADS RevB User’s Manual MOTOROLA
Operating Instructions
Warning
The initialization in TABLE 4-4. "Memory Control-
ler Initialization for 100(50) MHz" below are based
on design and are not verified yet, due to silicon
availability problems.
TABLE 4-4. Memory Controller Initialization for 100(50)
a
MHz
Reg. Device Type Bus
Init Value
[hex]
Description
BR0 SM73228XG1JHBG0 by
Smart Modular Tech.
Buffered
PPC
FF801801 Base at FF800000, 32 bit port size, no parity,
GPCM
SM73248XG2JHBG0 by
Smart Modular Tech.
FF001801 Base at FF00000, 32 bit port size, no parity,
GPCM
SM73288XG4JHBG0 by
Smart Modular Tech.
FE001801 Base at FE00000, 32 bit port size, no parity,
GPCM
OR0 SM73228XG1JHBG0 by
Smart Modular Tech.
FF800866
(FF800836)
8MByte block size, CS early negate, 12(6) w.s.,
Timing relax
SM73248XG2JHBG0 by
Smart Modular Tech.
FF000866
(FF000836)
16MByte block size, CS early negate, 12(6) w.s.,
Timing relax
SM73288XG4JHBG0 by
Smart Modular Tech.
FE000866
(FE000836)
32MByte block size, CS early negate, 12(6) w.s.,
Timing relax
BR1
BCSR0-3
Buffered
PPC
14501801 Base at 14500000, 32 bit port size, no parity,
GPCM
OR1 FFFF8010
(FFFF8020)
32 KByte block size, all types access, 1 w.s.
(32 KByte block size, all types access, 2 w.s.)
BR2 SDRAM 64bit Supported Non-buffered
PPC
20000041 Base at 20000000, 64 bit port size, no parity,
SDRAM machine 1
OR2 MT48LC2M32B2T6-8x2
by Micron
FF003080 16MByte block size, 4 banks per device, row starts
at A8, 11 row lines, internal bank interleaving
allowed
BR2
b
SDRAM 32bit Supported Non-buffered
PPC with
Host support
20001841 Base at 20000000, 32 bit port size, no parity,
SDRAM machine 1
OR2
b
MT48LC2M32B2T6-8 by
Micron
FF803280 8MByte block size, 4 banks per device, row starts
at A9, 11 row lines, internal bank interleaving
allowed
BR3
c
SDRAM 32bit Supported Non-buffered
PPC with
Host support
20801841 Base at 20800000, 32 bit port size, no parity,
SDRAM machine 1
OR3
c
MT48LC2M32B2T6-8 by
Micron
FF803280 8MByte block size, 4 banks per device, row starts
at A9, 11 row lines, internal bank interleaving
allowed
BR4 QFALC - 4ch. T1/E1 Buffered
PPC
146088A1 Base at 14608000, 8 bit port size, no parity, UPMB
on PPC bus
OR4 FFFF8106 32K Byte block size, burst inhibit, eight idle cycle
are inserted before next access
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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