B-84 MSC8101ADS RevB User’s Manual MOTOROLA
B2 ATMTCAb (PA30) I/O, T.S. ATM Transmit Cell Available (H). When this signal is asserted
(High), while the ATM port is enabled, it indicates that the transmit
FIFO of the PM5350 is empty and ready to except a new cell.
When negated, it may show either that the transmit FIFO is Full or
close to Full, depending on PM5350 internal programming.
When the ATM port is disabled, this line may be used for any
available function of PA30.
B3 ATMTSOC (PA29) I/O, T.S. ATM Transmit Start Of Cell (H). When this signal is asserted
(High) by the MSC8101, while the ATM port is enabled, it
indicates to the PM5350 the start of a new ATM cell over
ATMTXD(7:0), i.e., the 1’st octet is present there.
When the ATM port is disabled, this line may be used for any
available function of PA29.
B4 ATMRXENb (PA28) I/O, T.S. ATM Receive Enable (L). When this signal is asserted (Low),
while the ATM port is enabled and ATMRFCLK
b
goes high, on
octet of data is available at the PM5350’s ATMRXD(7:0) lines.
When negated while ATMRFCLK goes high data on
ATMRXD(7:0) is invalid, however driven.
When the ATM port is disabled, this line may be used for any
available function for PA28.
B5 ATMRSOC (PA27) I/O, T.S. ATM Receive Start Of Cell (H). When this signal is asserted
(High), while the ATM port is enabled, it indicates, that the 1’st
octet of data for the received cell is available at the PM5350’s
ATMRXD(7:0) lines. This line is updated over the rising edge of
ATMRFCLK.
When the ATM port is disabled, this line is tristated and may be
used for any available function for PA27.
B6 ATMRCA (PA26) I/O, T.S. ATM Receive Cell Available (H). When this signal is asserted
(High), while the ATM port is enabled and ATMRFCLK goes high,
it indicates that the PM5350’s receive FIFO is either full or that
there are 4 empty bytes left in it - PM5350 internal programming
dependent.
When the ATM port is disabled, this line is tristated and may be
used for any available function of PA26.
B7 ATMTXD0 (PA25) I/O, T.S. ATM Transmit Data (7
c
:0). When the ATM port is enabled, this
bus carries the ATM cell octets, written to the PM5350’s transmit
FIFO. This bus is considered valid only when ATMTXENb is
asserted and are sampled on the rising edge of ATMTFCLK.
When the ATM port is disabled, these lines may be used for any
available respective function.
B8 ATMTXD1 (PA24)
B9 ATMTXD2 (PA23)
B10 ATMTXD3 (PA22)
B11 ATMTXD4 (PA21)
B12 ATMTXD5 (PA20)
B13 ATMTXD6 (PA19)
B14 ATMTXD7 (PA18)
TABLE B1-3. P2 - CPM Expansion - Interconnect Signals
Pin No. Signal Name Attribute Description
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
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