Motorola MSC8101 ADS User Manual download pdf (Page 38)

38 MSC8101ADS RevB User’s Manual MOTOROLA

Operating Instructions

MBMR QFALC - 4ch. T1/E1

Read Access

Buffered

PPC

10015400 60x bus select, refresh disable, write to UPM

RAM, Read loop execute 5 times, first RAM

address.

Write Access 10015418 60x bus select, refresh disable, write to UPM

RAM, Write loop execute 5 times, RAM address

begins at 18H.

Exception Access 1001543c RAM address begins at 0x3c.

Normal Operation 00015400 Execute at 0x0.

a. Table values in parentheses reflect the lower frequency bus.

b. With Host Enable.

c. If additional SDRAM device U38SP will be assembled on the ADS (special requirement).

TABLE 4-4. Memory Controller Initialization for 100(50)

MHz

Reg. Device Type Bus

Init Value

[hex]

Description

Frees

cale Semiconductor,

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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Motorola MSC8101 ADS User Manual Page 38