Motorola M68CPU32BUG User Manual Page 92
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USER CUSTOMIZATION
M68CPU32BUG REV 1 C-8
Table C-1. CPU32Bug Customization Area (continued)
Offset Default Value Mnemonic Description
ROM AUTO BOOT VECTORS
$78-7B $FFFFFFFF RB_SP ROM auto boot stack pointer value
$7C-7F $FFFFFFFF RB_PC ROM auto boot program counter value:
Bit 0 = 1 disables auto boot (odd address)
= 0 enables auto boot (even address).
Enabling is equivalent to changing the stack
pointer (SP) and program counter (PC) and
entering the GO command. If any error was
detected during self-test (PWR_TST) the auto
boot is disabled.
CONSOLE DEFAULT TABLE FOR SCI (CONSCI)
$80-83 $00001C0F .PARMS Parameter definition for below:
Do not change this value.
$84-85 $2580 .BAUD Baud rate (in decimal):
19200 = $4B00
9600 = $2580
4800 = $12C0
2400 = $0960
1200 = $04B0
600 = $0258
300 = $012C
$86 $00 .PARITY Parity selection (see Table C-2):
None = $00
Even = $45 = ’E’
Odd = $4F = ’O’
$87 $08 .DATA Data bits (see Table C-2):
8-bits = $08
7-bits = $07
USER CUSTOMIZATION
M68CPU32BUG REV 1 C-9
Table C-1. CPU32Bug Customization Area (continued)
Offset Default Value Mnemonic Description
Console Default Table for SCI (CONSCI) (continued)
$88 $01 .STOP Stop bits (see Table C-2):
1-bit = $01
2-bit = $02
$89 $FF .XON_ENB XON/XOFF enable:
enable = $FF
disable = $00
$8A $11 .XON XON character (7-bit ASCII):
^Q = $11
$8B $13 .XOFF XOFF character (7-bit ASCII):
^S = $13
Periodic Interrupt Timer
$8C-8D $0642 .PICR Periodic interrupt control register value:
Default value is set for level 6, vect. 66.
$8E-8F $0102 .PITR Periodic interrupt timing register value:
Controls the "tick" time for the SYSCALL timing
functions ($4X). Default value is set for 125
milliseconds.
Fr
eescale S
emiconduct
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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- M68CPU32BUG DEBUG MONITOR 1
- USER’S MANUAL 1
- M68CPU32BUG/D 1
- TABLE OF CONTENTS 2
- LIST OF FIGURES 3
- LIST OF TABLES 3
- 1.5 SYSTEM RESTART 5
- CHAPTER 1 5
- GENERAL INFORMATION 5
- 1.1 INTRODUCTION 5
- 1.2 GENERAL DESCRIPTION 5
- 1.3 USING THIS MANUAL 6
- 1.6 MEMORY REQUIREMENTS 7
- CHAPTER 2 9
- DEBUG MONITOR DESCRIPTION 9
- 2.1 INTRODUCTION 9
- Freescale Semiconductor, Inc 10
- 2.6 FUNCTION CODE SUPPORT 13
- CHAPTER 3 16
- DEBUG MONITOR COMMANDS 16
- 3.1 INTRODUCTION 16
- BC Block of Memory Compare BC 17
- BF Block of Memory Fill BF 17
- BS Block of Memory Search BS 19
- BM Block of Memory Move BM 19
- BR Breakpoint Insert BR 20
- BV Block of Memory Verify BV 21
- DU Dump S-Records DU 23
- DC Data Conversion DC 23
- GN Go To Next Instruction GN 25
- GO Go Execute User Program GO 27
- HE Help HE 29
- MA Macro Define/Display MA 31
- MAE Macro Edit MAE 33
- MM Memory Modify MM 35
- MD Memory Display MD 36
- MS Memory Set MS 38
- PF Port Format PF 39
- PA Printer Attached PA 40
- RD Register Display RD 41
- RS Register Set RS 43
- RESET Cold/Warm Reset RESET 44
- RM Register Modify RM 44
- T Trace T 45
- SD Switch Directories SD 45
- TM Transparent Mode TM 48
- 4.2SOURCE PROGRAM CODING 51
- CHAPTER 4 52
- ASSEMBLER/DISASSEMBLER 52
- 4.1 INTRODUCTION 52
- 5.2 SYSTEM CALL ROUTINES 57
- CHAPTER 5 58
- SYSTEM CALLS 58
- 5.1 INTRODUCTION 58
- .ERASLN Erase Line .ERASLN 61
- .OUTSTR .OUTSTR 66
- .SNDBRK Send Break .SNDBRK 68
- .TM_RD Read Timer .TM_RD 70
- .WRITELN .WRITELN 71
- .WRITDLN .WRITDLN 71
- 6.3 UTILITIES 73
- CHAPTER 6 73
- DIAGNOSTIC FIRMWARE GUIDE 73
- 6.1 INTRODUCTION 73
- 6.2 DIAGNOSTIC MONITOR 73
- CPU B Instruction Test CPU B 75
- CPU CPU Tests For The MCU CPU 76
- CPU A Register Test CPU A 76
- CPU C Address Mode Test CPU C 77
- MT Memory Tests MT 78
- MT D Set Bus Data Width MT D 79
- MT A Set Function Code MT A 79
- MT B Set Start Address MT B 80
- MT C Set Stop Address MT C 80
- MT H Random Byte Test MT H 81
- MT E March Address Test MT E 81
- MT F Walk a Bit Test MT F 82
- MT G Refresh Test MT G 82
- MT I Program Test MT I 83
- MT J Test and Set Test MT J 84
- BERR Bus Error Test BERR 84
- APPENDIX A 85
- S-RECORD INFORMATION 85
- A.1 INTRODUCTION 85
- A.2 S-RECORD CONTENT 85
- A.3 S-RECORD TYPES 86
- A.4 S-RECORDS CREATION 86
- C.2 CPU32BUG CUSTOMIZATION 87
- APPENDIX B 87
- SELF-TEST ERROR MESSAGES 87
- B.1 INTRODUCTION 87
- APPENDIX C 88
- USER CUSTOMIZATION 88
- C.1 INTRODUCTION 88
- C.3 CUSTOMIZATION TABLE 90
- C.4 COMMUNICATION FORMATS 93
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