Motorola M68CPU32BUG User Manual Page 14
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DEBUG MONITOR DESCRIPTION
M68CPU32BUG/D REV 1 2-10
2.5.2.2 Creating Vector Tables
A user program may create a separate vector table to store its exception vectors. If this is done,
the user program must change the value of the vector base register to point to the new vector
table. To use the debugger facilities, copy the vectors from the CPU32Bug vector table into the
corresponding user vector table locations (block of memory move (BM) command).
The vector for the CPU32Bug generalized exception handler (described in detail in paragraph
2.5.2.3) may be copied from offset $08 (Bus Error vector) in the target-vector table to all
locations in the user’s vector table where a separate exception handler is not used. This provides
diagnostic support in the event execution of the user program is terminated by an unexpected
exception. The generalized exception handler gives a formatted display of the target registers and
identifies the type of the exception.
The following is an example of a user routine which builds a separate vector table and then sets
the vector base register to point at it.
*
*** BUILDX
– Build exception vector table ***
*
BUILDX MOVEC.L VBR,A0
Get copy of VBR.
LEA $1 0000,A1
New vectors at $10000.
MOVE.L $8(A0),D0
Get generalized exception vector.
MOVE.W $3FC,D1
Load count (all vectors).
LOOP MOVE.L D0,(A1,D1)
Store generalized exception vector.
SU BQ.W #4, D 1
BPL.B LOOP
Initialize entire vector table.
MOVE.L $1 0(A0),$1 0(A1 )
Copy breakpoints vector.
MOVE.L $24(A0),$24(A1 )
Copy trace vector.
MOVE.L $BC(A0),$BC(A1 )
Copy system call vector.
LEA.L TIMER(PC),A2
Get user exception vector.
MOVE.L A2,$2C(A1 )
Install as F-Line handler.
MOVEC.L A1 ,VBR
Change VBR to new table.
RTS
END
The user program may use one or more of the exception vectors that are required for debugger
operation if the user’s exception handler can determine when to handle the exception itself and
when to pass the exception to the debugger.
When an exception occurs which requires debugger operation (i.e., ABORT), the user’s
exception handler must read the vector offset from the exception-stack-frame format word. This
offset is added to the address of the CPU32Bug target program vector table (which the user
program saves), producing the address of the CPU32Bug exception vector. The user program
then jumps to the address stored at this vector location (i.e., which is the address of the
CPU32Bug exception handler).
The user program must ensure an exception stack frame is in the stack and that it is identical to
one the processor would create for the particular exception. It may then jump to the address of
the exception handler.
DEBUG MONITOR DESCRIPTION
M68CPU32BUG/D REV 1 2-11
EXAMPLE The user exception handler passes an exception along to the debugger.
*
*** EXCEPT - Exception handler ****
*
EXCEPT SUBQ.L #4,A7
Save space in stack for a PC value.
LINK A6,#0
Frame pointer for accessing PC space.
MOVEM.L A0-A5/D0-D7,-(A7)
Save registers.
: decide here if user code will handle exception, if so, branch...
MOVE.L BUFVBR,A0
Pass exception to debugger; Get VBR.
MOVE.W 14(A6), Do
Get the vector offset from stack frame.
AND.W #$0FFF,D0
Mask off the format information.
MOVE.L (A0,D0.W),4(A6)
Store address of debugger exception handler.
UNLK
A6
RTS
Put address of exception handler into PC and go.
2.5.2.3 CPU32Bug Generalized Exception Handler
The CPU32Bug generalized exception handler supervises all exceptions not listed in Table 2-2.
For these exceptions, the target stack pointer points to the top of the user exception stack frame.
In this way, if an unexpected exception occurs during user code segment execution, the exception
stack frame displays to assist in determining the cause of the exception.
EXAMPLE Bus error at address $F00000. It is assumed for this example that an access
of memory location $F00000 initiates bus error exception processing.
CPU32Bug>RD<CR>
PC =00003000 SR =2700=TR:OFF_S_7_.... VBR =00000000
SFC =5=SD DFC =5=SD USP =0000FC00 SSP* =00004000
D0 =00000000 D1 =00000000 D2 =00000000 D3 =00000000
D4 =00000000 D5 =00000000 D6 =00000000 D7 =00000000
A0 =00000000 A1 =00000000 A2 =00000000 A3 =00000000
A4 =00000000 A5 =00000000 A6 =00000000 A7 =00004000
00003000 203900F0 0000 MOVE.L ($F00000).L,D0
CPU32Bug>T<CR>
Exception: Bus Error
Format/Vector=C008
SSW=0065 Fault Addr.=00F00000 Data=FFFF3000 Cur. PC=00003000 Cnt. Reg.=0001
PC =00003000 SR =A700=TR:ALL_S_7_.... VBR =00000000
SFC =5=SD DFC =5=SD USP =0000FC00 SSP* =00003FE8
D0 =00000000 D1 =00000000 D2 =00000000 D3 =00000000
D4 =00000000 D5 =00000000 D6 =00000000 D7 =00000000
A0 =00000000 A1 =00000000 A2 =00000000 A3 =00000000
A4 =00000000 A5 =00000000 A6 =00000000 A7 =00003FE8
00003000 203900F0 0000 MOVE.L ($F00000).L,D0
CPU32Bug>
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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- M68CPU32BUG DEBUG MONITOR 1
- USER’S MANUAL 1
- M68CPU32BUG/D 1
- TABLE OF CONTENTS 2
- LIST OF FIGURES 3
- LIST OF TABLES 3
- 1.5 SYSTEM RESTART 5
- CHAPTER 1 5
- GENERAL INFORMATION 5
- 1.1 INTRODUCTION 5
- 1.2 GENERAL DESCRIPTION 5
- 1.3 USING THIS MANUAL 6
- 1.6 MEMORY REQUIREMENTS 7
- CHAPTER 2 9
- DEBUG MONITOR DESCRIPTION 9
- 2.1 INTRODUCTION 9
- Freescale Semiconductor, Inc 10
- 2.6 FUNCTION CODE SUPPORT 13
- CHAPTER 3 16
- DEBUG MONITOR COMMANDS 16
- 3.1 INTRODUCTION 16
- BC Block of Memory Compare BC 17
- BF Block of Memory Fill BF 17
- BS Block of Memory Search BS 19
- BM Block of Memory Move BM 19
- BR Breakpoint Insert BR 20
- BV Block of Memory Verify BV 21
- DU Dump S-Records DU 23
- DC Data Conversion DC 23
- GN Go To Next Instruction GN 25
- GO Go Execute User Program GO 27
- HE Help HE 29
- MA Macro Define/Display MA 31
- MAE Macro Edit MAE 33
- MM Memory Modify MM 35
- MD Memory Display MD 36
- MS Memory Set MS 38
- PF Port Format PF 39
- PA Printer Attached PA 40
- RD Register Display RD 41
- RS Register Set RS 43
- RESET Cold/Warm Reset RESET 44
- RM Register Modify RM 44
- T Trace T 45
- SD Switch Directories SD 45
- TM Transparent Mode TM 48
- 4.2SOURCE PROGRAM CODING 51
- CHAPTER 4 52
- ASSEMBLER/DISASSEMBLER 52
- 4.1 INTRODUCTION 52
- 5.2 SYSTEM CALL ROUTINES 57
- CHAPTER 5 58
- SYSTEM CALLS 58
- 5.1 INTRODUCTION 58
- .ERASLN Erase Line .ERASLN 61
- .OUTSTR .OUTSTR 66
- .SNDBRK Send Break .SNDBRK 68
- .TM_RD Read Timer .TM_RD 70
- .WRITELN .WRITELN 71
- .WRITDLN .WRITDLN 71
- 6.3 UTILITIES 73
- CHAPTER 6 73
- DIAGNOSTIC FIRMWARE GUIDE 73
- 6.1 INTRODUCTION 73
- 6.2 DIAGNOSTIC MONITOR 73
- CPU B Instruction Test CPU B 75
- CPU CPU Tests For The MCU CPU 76
- CPU A Register Test CPU A 76
- CPU C Address Mode Test CPU C 77
- MT Memory Tests MT 78
- MT D Set Bus Data Width MT D 79
- MT A Set Function Code MT A 79
- MT B Set Start Address MT B 80
- MT C Set Stop Address MT C 80
- MT H Random Byte Test MT H 81
- MT E March Address Test MT E 81
- MT F Walk a Bit Test MT F 82
- MT G Refresh Test MT G 82
- MT I Program Test MT I 83
- MT J Test and Set Test MT J 84
- BERR Bus Error Test BERR 84
- APPENDIX A 85
- S-RECORD INFORMATION 85
- A.1 INTRODUCTION 85
- A.2 S-RECORD CONTENT 85
- A.3 S-RECORD TYPES 86
- A.4 S-RECORDS CREATION 86
- C.2 CPU32BUG CUSTOMIZATION 87
- APPENDIX B 87
- SELF-TEST ERROR MESSAGES 87
- B.1 INTRODUCTION 87
- APPENDIX C 88
- USER CUSTOMIZATION 88
- C.1 INTRODUCTION 88
- C.3 CUSTOMIZATION TABLE 90
- C.4 COMMUNICATION FORMATS 93
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