Motorola M68CPU32BUG User Manual Page 4
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TABLE OF CONTENTS
M68CPU32BUG/D REV 1 iv
CHAPTER 6 DIAGNOSTIC FIRMWARE GUIDE
6.1 Introduction......................................................................................................................... 6-1
6.2 Diagnostic Monitor............................................................................................................. 6-1
6.2.1 Monitor Start-Up...................................................................................................... 6-1
6.2.2 Command Entry and Directories.............................................................................. 6-1
6.2.3 Help (HE)................................................................................................................. 6-2
6.2.4 Self Test (ST) ........................................................................................................... 6-2
6.2.5 Switch Directories (SD) ........................................................................................... 6-2
6.2.6 Loop-On-Error Mode (LE)....................................................................................... 6-2
6.2.7 Stop-On-Error Mode (SE)........................................................................................ 6-3
6.2.8 Loop-Continue Mode (LC)....................................................................................... 6-3
6.2.9 Non-Verbose Mode (NV)......................................................................................... 6-3
6.2.10 Display Error Counters (DE).................................................................................... 6-3
6.2.11 Clear (Zero) Error Counters (ZE)............................................................................. 6-3
6.2.12 Display Pass Count (DP).......................................................................................... 6-3
6.2.13 Zero Pass Count (ZP)............................................................................................... 6-4
6.3 Utilities ............................................................................................................................... 6-4
6.3.1 Write Loop ............................................................................................................... 6-4
6.3.2 Read Loop ................................................................................................................ 6-5
6.3.3 Write/Read Loop...................................................................................................... 6-5
6.4 CPU Tests For The MCU (CPU)........................................................................................ 6-6
6.4.1 Register Test (CPU A) ............................................................................................. 6-7
6.4.2 Instruction Test (CPU B).......................................................................................... 6-8
6.4.3 Address Mode Test (CPU C).................................................................................... 6-9
6.4.4 Exception Processing Test (CPU D)...................................................................... 6-10
6.5 Memory Tests (MT).......................................................................................................... 6-11
6.5.1 Set Function Code (MT A)..................................................................................... 6-13
6.5.2 Set Start Address (MT B)....................................................................................... 6-14
6.5.3 Set Stop Address (MT C)....................................................................................... 6-15
6.5.4 Set Bus Data Width (MT D)................................................................................... 6-16
6.5.5 March Address Test (MT E)................................................................................... 6-17
6.5.6 Walk a Bit Test (MT F).......................................................................................... 6-18
6.5.7 Refresh Test (MT G).............................................................................................. 6-19
6.5.8 Random Byte Test (MT H)..................................................................................... 6-20
6.5.9 Program Test (MT I) .............................................................................................. 6-21
6.5.10 Test and Set Test (MT J)........................................................................................ 6-22
6.6 Bus Error Test (BERR)..................................................................................................... 6-23
TABLE OF CONTENTS
M68CPU32BUG/D REV 1 v
APPENDIX A S-RECORD INFORMATION
A.1 Introduction.........................................................................................................................A-1
A.2 S-Record Content................................................................................................................A-1
A.3 S-Record Types...................................................................................................................A-2
A.4 S-Records Creation.............................................................................................................A-3
APPENDIX B SELF-TEST ERROR MESSAGES
B.1 Introduction.........................................................................................................................B-1
APPENDIX C USER CUSTOMIZATION
C.1 Introduction.........................................................................................................................C-1
C.2 CPU32BUG Customization................................................................................................C-2
C.3 Customization Table...........................................................................................................C-5
C.4 Communication Formats ..................................................................................................C-14
C.5 BCC REV. A Chip Selection Summary...........................................................................C-15
C.6 BCC REV. B Chip Selection Summary............................................................................C-16
C.7 BCC REV. C Chip Selection Summary ...........................................................................C-17
C.8 Platform Board (PFB) REV. C Compatibility..................................................................C-18
C.9 CPU32BUG Questions and Answers ...............................................................................C-19
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- M68CPU32BUG DEBUG MONITOR 1
- USER’S MANUAL 1
- M68CPU32BUG/D 1
- TABLE OF CONTENTS 2
- LIST OF FIGURES 3
- LIST OF TABLES 3
- 1.5 SYSTEM RESTART 5
- CHAPTER 1 5
- GENERAL INFORMATION 5
- 1.1 INTRODUCTION 5
- 1.2 GENERAL DESCRIPTION 5
- 1.3 USING THIS MANUAL 6
- 1.6 MEMORY REQUIREMENTS 7
- CHAPTER 2 9
- DEBUG MONITOR DESCRIPTION 9
- 2.1 INTRODUCTION 9
- Freescale Semiconductor, Inc 10
- 2.6 FUNCTION CODE SUPPORT 13
- CHAPTER 3 16
- DEBUG MONITOR COMMANDS 16
- 3.1 INTRODUCTION 16
- BC Block of Memory Compare BC 17
- BF Block of Memory Fill BF 17
- BS Block of Memory Search BS 19
- BM Block of Memory Move BM 19
- BR Breakpoint Insert BR 20
- BV Block of Memory Verify BV 21
- DU Dump S-Records DU 23
- DC Data Conversion DC 23
- GN Go To Next Instruction GN 25
- GO Go Execute User Program GO 27
- HE Help HE 29
- MA Macro Define/Display MA 31
- MAE Macro Edit MAE 33
- MM Memory Modify MM 35
- MD Memory Display MD 36
- MS Memory Set MS 38
- PF Port Format PF 39
- PA Printer Attached PA 40
- RD Register Display RD 41
- RS Register Set RS 43
- RESET Cold/Warm Reset RESET 44
- RM Register Modify RM 44
- T Trace T 45
- SD Switch Directories SD 45
- TM Transparent Mode TM 48
- 4.2SOURCE PROGRAM CODING 51
- CHAPTER 4 52
- ASSEMBLER/DISASSEMBLER 52
- 4.1 INTRODUCTION 52
- 5.2 SYSTEM CALL ROUTINES 57
- CHAPTER 5 58
- SYSTEM CALLS 58
- 5.1 INTRODUCTION 58
- .ERASLN Erase Line .ERASLN 61
- .OUTSTR .OUTSTR 66
- .SNDBRK Send Break .SNDBRK 68
- .TM_RD Read Timer .TM_RD 70
- .WRITELN .WRITELN 71
- .WRITDLN .WRITDLN 71
- 6.3 UTILITIES 73
- CHAPTER 6 73
- DIAGNOSTIC FIRMWARE GUIDE 73
- 6.1 INTRODUCTION 73
- 6.2 DIAGNOSTIC MONITOR 73
- CPU B Instruction Test CPU B 75
- CPU CPU Tests For The MCU CPU 76
- CPU A Register Test CPU A 76
- CPU C Address Mode Test CPU C 77
- MT Memory Tests MT 78
- MT D Set Bus Data Width MT D 79
- MT A Set Function Code MT A 79
- MT B Set Start Address MT B 80
- MT C Set Stop Address MT C 80
- MT H Random Byte Test MT H 81
- MT E March Address Test MT E 81
- MT F Walk a Bit Test MT F 82
- MT G Refresh Test MT G 82
- MT I Program Test MT I 83
- MT J Test and Set Test MT J 84
- BERR Bus Error Test BERR 84
- APPENDIX A 85
- S-RECORD INFORMATION 85
- A.1 INTRODUCTION 85
- A.2 S-RECORD CONTENT 85
- A.3 S-RECORD TYPES 86
- A.4 S-RECORDS CREATION 86
- C.2 CPU32BUG CUSTOMIZATION 87
- APPENDIX B 87
- SELF-TEST ERROR MESSAGES 87
- B.1 INTRODUCTION 87
- APPENDIX C 88
- USER CUSTOMIZATION 88
- C.1 INTRODUCTION 88
- C.3 CUSTOMIZATION TABLE 90
- C.4 COMMUNICATION FORMATS 93
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