Motorola M68CPU32BUG User Manual Page 15
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DEBUG MONITOR COMMANDS
M68CPU32BUG/D REV 1 3-2
Table 3-1. Debug Monitor Commands (continued)
Command
Mnemonic Title Paragraph
OF Offset Registers Display/Modify 3.22
PA/NOPA Printer Attach/Detach 3.23
PF Port Format 3.24
RD Register Display 3.25
RESET Cold/Warm Reset 3.26
RM Register Modify 3.27
RS Register Set 3.28
SD Switch Directories 3.29
T Trace 3.30
TC Trace On Change of Control Flow 3.31
TM Transparent Mode 3.32
TT Trace To Temporary Breakpoint 3.33
VE Verify S-Records Against Memory 3.34
Each command is described in the following text. Command syntax symbols are explained in
section 2.1. In the examples of the debugger commands all user inputs are in bold type. This
helps clarify examples by distinguishing user input characters from CPU32Bug output characters.
The symbol <CR> represents the carriage return key on the user’s terminal keyboard. This
symbol indicates the user should enter a carriage return.
DEBUG MONITOR DESCRIPTION
M68CPU32BUG/D REV 1 2-13
The valid function code mnemonics are:
Function Code Mnemonic Description
0 F0 Unassigned, reserved
1 UD User Data
2 UP User Program
3 F3 Unassigned, reserved
4 F4 Unassigned, reserved
5 SD Supervisor Data
6 SP Supervisor Program
7 CS CPU Space Cycle
The BR, GD, GO, and GT commands set the valid function codes to either a user program (UP)
or supervisor program (SP). When execution is started via GO, GN, or GD, the default address
space is determined by bit 13 (the S-bit) of the status register (SR). When set, SP is used; when
cleared, UP is used. By specifying a function code with GO, GT, or GD command, the SR S-bit
is forced to the correct state before execution begins.
For the GT command, the temporary breakpoint is set using the function code specified, or it
defaults to SP or UP, depending on the state of the S-bit in the SR.
Though function codes are supported, the BCC hardware does not require function codes to
operate.
EXAMPLE To change data at location $5000 in the user data space.
CPU32Bug>m 5000^ud<CR>
00005000^UD 0000 ? 1234.<CR>
CPU32Bug>
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Freescale Semiconductor, Inc.
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- M68CPU32BUG DEBUG MONITOR 1
- USER’S MANUAL 1
- M68CPU32BUG/D 1
- TABLE OF CONTENTS 2
- LIST OF FIGURES 3
- LIST OF TABLES 3
- 1.5 SYSTEM RESTART 5
- CHAPTER 1 5
- GENERAL INFORMATION 5
- 1.1 INTRODUCTION 5
- 1.2 GENERAL DESCRIPTION 5
- 1.3 USING THIS MANUAL 6
- 1.6 MEMORY REQUIREMENTS 7
- CHAPTER 2 9
- DEBUG MONITOR DESCRIPTION 9
- 2.1 INTRODUCTION 9
- Freescale Semiconductor, Inc 10
- 2.6 FUNCTION CODE SUPPORT 13
- CHAPTER 3 16
- DEBUG MONITOR COMMANDS 16
- 3.1 INTRODUCTION 16
- BC Block of Memory Compare BC 17
- BF Block of Memory Fill BF 17
- BS Block of Memory Search BS 19
- BM Block of Memory Move BM 19
- BR Breakpoint Insert BR 20
- BV Block of Memory Verify BV 21
- DU Dump S-Records DU 23
- DC Data Conversion DC 23
- GN Go To Next Instruction GN 25
- GO Go Execute User Program GO 27
- HE Help HE 29
- MA Macro Define/Display MA 31
- MAE Macro Edit MAE 33
- MM Memory Modify MM 35
- MD Memory Display MD 36
- MS Memory Set MS 38
- PF Port Format PF 39
- PA Printer Attached PA 40
- RD Register Display RD 41
- RS Register Set RS 43
- RESET Cold/Warm Reset RESET 44
- RM Register Modify RM 44
- T Trace T 45
- SD Switch Directories SD 45
- TM Transparent Mode TM 48
- 4.2SOURCE PROGRAM CODING 51
- CHAPTER 4 52
- ASSEMBLER/DISASSEMBLER 52
- 4.1 INTRODUCTION 52
- 5.2 SYSTEM CALL ROUTINES 57
- CHAPTER 5 58
- SYSTEM CALLS 58
- 5.1 INTRODUCTION 58
- .ERASLN Erase Line .ERASLN 61
- .OUTSTR .OUTSTR 66
- .SNDBRK Send Break .SNDBRK 68
- .TM_RD Read Timer .TM_RD 70
- .WRITELN .WRITELN 71
- .WRITDLN .WRITDLN 71
- 6.3 UTILITIES 73
- CHAPTER 6 73
- DIAGNOSTIC FIRMWARE GUIDE 73
- 6.1 INTRODUCTION 73
- 6.2 DIAGNOSTIC MONITOR 73
- CPU B Instruction Test CPU B 75
- CPU CPU Tests For The MCU CPU 76
- CPU A Register Test CPU A 76
- CPU C Address Mode Test CPU C 77
- MT Memory Tests MT 78
- MT D Set Bus Data Width MT D 79
- MT A Set Function Code MT A 79
- MT B Set Start Address MT B 80
- MT C Set Stop Address MT C 80
- MT H Random Byte Test MT H 81
- MT E March Address Test MT E 81
- MT F Walk a Bit Test MT F 82
- MT G Refresh Test MT G 82
- MT I Program Test MT I 83
- MT J Test and Set Test MT J 84
- BERR Bus Error Test BERR 84
- APPENDIX A 85
- S-RECORD INFORMATION 85
- A.1 INTRODUCTION 85
- A.2 S-RECORD CONTENT 85
- A.3 S-RECORD TYPES 86
- A.4 S-RECORDS CREATION 86
- C.2 CPU32BUG CUSTOMIZATION 87
- APPENDIX B 87
- SELF-TEST ERROR MESSAGES 87
- B.1 INTRODUCTION 87
- APPENDIX C 88
- USER CUSTOMIZATION 88
- C.1 INTRODUCTION 88
- C.3 CUSTOMIZATION TABLE 90
- C.4 COMMUNICATION FORMATS 93
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