Motorola DSP56305 User Manual Page 82

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Pipeline Interlocks
Program Flow-Control Pipeline Interlocks
MOTOROLA Optimizing DSP56300/DSP56600 Applications 6-9
hardware stack so that it will not be full or empty and the execution
of instructions can continue. This activity of the stack extension
delays the execution phases by the number of cycles required to
move data to or from the stack, usually two cycles for each move.
6.3.1 Stack Extension Full/Empty Cases
The stack-full or stack-empty states are defined by the contents of
the SC (Stack Counter) register. When the stack counter equals 14, it
means that the on-chip hardware stack has fourteen words (a stack
word is a 48-bit long word combined from the low and the high
portions of the stack) inside. The stack is declared as stack-full, and
any additional push operation will activate the stack extension
mechanism. When the stack counter equals 2, it means that the
on-chip hardware stack has only two words inside. The stack is
declared as stack-empty, and any additional pop operation will
activate the stack extension mechanism.
6.3.2 Avoiding Stack Extension Delays
The best way to avoid stack extension delays is to make sure that
the number of stack levels used during execution of critical code
segments will not be larger than fourteen. If this is the case, and
upon entry to this piece of code, the stack was empty, absolutely no
stack extension delays will be added to the program flow. If
however, the stack was not empty, few stack extension delays will
be added until the code has reached its upper stack level.
6.4 PROGRAM FLOW-CONTROL PIPELINE
INTERLOCKS
During the execution of flow-control instructions, some boundary
non-frequent cases exist and introduce interlocks to the program
flow. These cases represent very unusual operations which
probably would never be used in a usual code. The generation of
interlock cycles in these cases is done in order to maintain object
code compatibility to the DSP56000 family of Digital Signal
Processors.
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