Motorola DSP56305 User Manual Page 78

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Pipeline Interlocks
Data ALU Pipeline Interlocks
MOTOROLA Optimizing DSP56300/DSP56600 Applications 6-5
The read operations in the tenth and eleventh instructions will not
cause arithmetic pipeline interlocks to happen. Although the loop
contains double the words of the original code, it is executed half
the time, resulting in 2N cycles performance as desired.
6.1.2.2.2 Unrolling in Memory Array Copy routine
The following code segment is used to copy data array (of N words)
from x-space memory to y-space memory:
move #X-start,r0 ;starting address of source
;array in x-memory
move #Y-start,r4 ;starting address of
;destination array in y-memory
DO #N,_end
move x:(r0)+,x0 ;read source array
move x0,y:(r4)+ ;write destination memory
_end
The main loop in the above code will be executed in 2N cycles. The
first stage towards optimization of this task would be to unroll the
loop while using double parallel moves:
move #X-start,r0 ;starting address of source
;array in x-memory
move #Y-start,r4 ;starting address of
;destination array in y-memory
move x:(r0)+,a ;read first word from source
;memory
DO #(N/2-1),_end
move x:(r0)+,aa,y:(r4)+ ;read source array, write
;previous data
move x:(r0)+,aa,y:(r4)+ ;write destination memory,
;read next data
_end
move a,y:(r4)+ ;write last word to destination
;memory
Please note that a transfer pipeline interlock is introduced in this
optimized code, causing the main loop to execute in 1.5N – 1 cycles.
The next step in optimizing the task would be to use both A and B to
avoid the transfer pipeline interlock. Using the following
modification, the main loop will execute in N – 1 cycles.
move #X-start,r0 ;starting address of source
;array in x-memory
move #Y-start,r4 ;starting address of
;destination array in y-memory
move x:(r0)+,a ;read first word from source
;memory
move x:(r0)+,b ;read second word from source
;memory
DO #(N/2-1),_end
move x:(r0)+,aa,y:(r4)+ ;read source array, write
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