Motorola DSP56305 User Manual download pdf (Page 57)

4-8 Optimizing DSP56300/DSP56600 Applications MOTOROLA

Using the DMA

Servicing a Peripheral

Note: Before servicing the data processing interrupt after the buffer

was filled, the core does not allocate any resource (registers

or processing time) to service the data acquisition that is

going on in the background.

The DMA flexible addressing modes can also be used to support

special data structures and I/O mapped addresses. Consider the

SCI, which can only transmit and receive serial data that is 8-bit

long. When transmitting a 24-bit word, it should write to three

transmit registers, each of which loads and transmits one byte

(STXL,STXM,STXH).

The core operations needed to initiate one 24-bit transfer are:

movep x:(r0),x:M_STXL;transmit low byte. r0 points

;to the data source

movep x:(r0),x:M_STXM;transmit middle byte.

movep x:(r0),x:M_STXH;transmit high byte.

Similarly, when receiving 24-bit data, the SCI should be read from

three receive registers (SRXL,SRXM,SRXH).The byte that is read is

positioned in the 24-bit data bus accordingly, the other two bytes

read as zeros. Therefore, the three words that were read must be

OR-ed to give the 24-bit data.

The basic DMA addressing scheme needed for transmitting one

24-bit word from the DSP56300 is a block of three transfers used to

write the three bytes of the original word. The source address is not

incremented, and the destination (SCI side) is defined as a 3-word

circular buffer, mapped on STXL,STXM,STXH.

There are a few options to define the next hierarchy—feeding

consecutive 24-bit words for transfer:

• A core interrupt that is triggered by the end of the 3-word

transfer—The interrupt writes the next data to the fixed

DMA source location. The core may define a circular data

buffer using AGU Modulo modes. The DMA can use the

mode that does not clear the DE bit at the end (Mode 100),

thus enabling the core to use a fast interrupt for that task (no

need to re-trigger the DMA channel). This is on condition

that interrupt service could be guaranteed in the time the SCI

is transferring the last byte. The “cost” of this option is one

DMA channel, one offset register, two AGU registers (Rx,

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Motorola DSP56305 User Manual Page 57