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Interrupt Handling Functional Description
CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)
85
4.4.2.1 MV64360 Interrupt Controller
The CPCI-6115 uses the MV64360 interrupt controller to route internal and external interrupt
requests to the CPU and the PCI bus. The MV64360 interrupt controller registers are
implemented as part of the CPU interface unit in order to have minimum read latency from CPU
interrupt handler. The external interrupt sources use the GPP interface to register external
interrupts. The following table shows the CPCI-6115 interrupt assignment to MV64360 GPP
pins:
These notes apply to Table 4-7.
1. The interrupting device is addressed from the MV64360 PCI Bus 0.0.
2. The interrupting device is addressed from the MV64360 PCI Bus 1.0
Table 4-7 MV64360 Interrupt Assignments
GPP
Group MV64360
Edge/L
evel Polarity Interrupt Source Notes
0 GPP[0] Level High COM1 || COM2 3
GPP[1] Level Low Unused
GPP[2] Level Low ABORT#
GPP[3] Level Low RTC || Thermostat output 6
GPP[4] Level Low Unused
GPP[5] Level Low Unused
GPP[6] Level Low MV64360 WDNMI# interrupt
GPP[7] Level Low BCM5421S PHY 1 INTR# || BCM5421S
PHY 2 INTR# || BCM5421S PHY 3 INTR#
2 GPP[16] Level Low PCI Bus 1.0 - PMC1 INTA#, PMC1 INTC#,
21555
2
GPP[17] Level Low PCI Bus 1.0 - PMC1 INTB#, PMC1 INTD#,
IDE
2
GPP[18] Level Low PCI Bus 0.0 - PMC2 INTA#, PMC2 INTC# 1
GPP[19] Level Low PCI Bus 0.0 - PMC2 INTB#, PMC2 INTD# 1
GPP[20] Level Low CompactPCI Bus - INTA# 5
GPP[21] Level Low CompactPCI Bus - INTB# 5
GPP[22] Level Low CompactPCI Bus - INTC# 5
GPP[23] Level Low CompactPCI Bus - INTD# 5
3 GPP[24] Reserved for SROM initialization active
InitAct output
GPP[25] Reserved for Watchdog Timer WDE#
output
GPP[26] Reserved for Watchdog Timer WDNMI#
output
GPP[27] Reserved for future device interrupt
- CPCI-6115 CompactPCI 1
- Single Board Computer 1
- Trademarks 2
- Contents 3
- List of Tables 10
- List of Figures 11
- About this Manual 13
- Abbreviations 14
- Conventions 16
- Summary of Changes 17
- Comments and Suggestions 18
- Safety Notes 19
- Operation 20
- Installation 20
- Cabling and Connectors 21
- Environment 22
- Sicherheitshinweise 23
- Schaltereinstellungen/Jumper 24
- Kabel und Stecker 26
- Umweltschutz 26
- Batterie 26
- Introduction 27
- 1.2 Standard Compliances 28
- 1.3 Ordering Information 29
- 2.1 Overview 31
- Requirements 32
- 2.3.2 Power Requirements 34
- 2.3.3 Thermal Requirements 34
- 2.4 Getting Started 37
- 2.5 Baseboard Preparation 38
- 2.5.3 J6, Bus Mode Selection 40
- 2.5.7 J20, Safe Start Header 42
- 2.6 Operating Modes 44
- 2.7 Installing Hardware 44
- Procedure 45
- Personal Injury or Death 46
- 2.9 Applying Power 49
- 3.1 Overview 51
- 3.2 Board Layout 52
- 3.4 ABORT/Reset Switch 54
- 3.5.7 CompactPCI Connector 58
- PCI_RSVD = PCI Reserved pin 62
- 3.5.14 Safe Start Header 67
- 3.5.15 Bus Mode Select Header 67
- 3.5.18 +/-12 V Present Header 68
- Functional Description 69
- 4.2 Block Diagram 70
- 4.3 General Description 71
- 4.3.2 Processor 72
- 4.3.3 L3 Cache 72
- 4.3.4.12 Interrupt Controller 76
- 4.3.4.13 PCI Bus Arbitration 76
- 4.3.4.14 Board Reset Logic 77
- 4.3.5 System Memory 81
- 4.3.6 Flash Memory 82
- 4.3.8 TL16C550C UART Devices 83
- 4.3.9 System Registers 83
- 4.3.10 Serial EEPROM Devices 83
- 4.3.11 PCI Bus 0.0 83
- 4.3.12 PCI Bus 1.0 83
- 4.3.13 IDE Controller 84
- 4.3.15 CompactPCI Bus 84
- 4.3.16 PMC Slots 84
- 4.4 Miscellaneous 86
- 4.4.3 Onboard Power Supplies 89
- 4.4.4 Hot Swap Support 89
- 4.4.5 Hot Swap Process 89
- 5.2 Block Diagram 92
- 5.4 Rear Panel Connectors 94
- 5.5.2.1 Host IO Connectors 96
- 5.5.2.2 PMC I/O Connectors 98
- 5.6 Jumper Settings 104
- 5.7 Functional Description 105
- 5.7.3 Hot-Swap Support 106
- 5.7.4 Serial EEPROM 106
- 5.7.5 PMC I/O Modules 106
- 5.7.7 PMC I/O Module 110
- 5.7.9 PMC I/O Connector 112
- 5.7.10 Host I/O Connector 112
- 5.8 Installing the PIM 113
- Figure 5-9 Installing the PIM 114
- Remote Start via the PCI Bus 117
- MOTLoad Firmware 119
- 7.4 MOTLoad Commands 120
- 7.6 MOTLoad Tests 120
- 7.7 Using MOTLoad 121
- 7.7.2 Command Line Help 122
- 7.7.3 Command Line Rules 122
- 7.8 MOTLoad Command List 123
- Memory Maps 127
- 8.2.2 Processor Memory Map 128
- 8.2.3 Default PCI Memory Map 129
- 8.2.5 System I/O Memory Map 131
- 8.2.7 CompactPCI Memory Map 131
- 8.2.9 L1, L2 and L3 Cache 132
- 8.2.10 System Memory 132
- A Related Documentation 133
- A.3 Related Specifications 134
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