Motorola CPCI-6115 Service Manual Page 57
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CompactPCI User I/O Connector Controls, LEDs, and Connectors
CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)
55
3.5.6 CompactPCI User I/O Connector
Connector J3 is a 110 pin AMP Z-pack 2mm hard metric type B connector. This connector
routes the I/O signals for one of the PMC slots and two 10/100/1000Base-T Ethernet channels
compliant with the CompactPCI Packet Switching Backplane Specification. The pin
assignments for J3 are as follows:
(Note that outer row F is assigned and used as ground pins but is not shown in the table).
19 GND GND RSV RSV RSV
18 BRSVP2A18 BRSVP2B18 BRSVP2C18 GND BRSVP2E18
17 BRSVP2A17 GND RSV RSV RSV
16 BRSVP2A16 BRSVP2B16 RSV GND BRSVP2E16
15 BRSVP2A15 GND RSV RSV RSV
14 AD[35] AD[34] AD[33] GND AD[32]
13 AD[38] GND V(IO) AD[37] AD[36]
12 AD[42] AD[41] AD[40] GND AD[39]
11 AD[45] GND V(IO) AD[44] AD[43]
10 AD[49] AD[48] AD[47] GND AD[46]
9 AD[52] GND V(IO) AD[51] AD[50]
8 AD[56] AD[55] AD[54] GND AD[53]
7 AD[59] GND V(IO) AD[58] AD[57]
6 AD[63] AD[62] AD[61] GND AD[60]
5 C/BE[5]# 64EN# V(IO) C/BE[4]# PAR64
4 V(IO) BRSVP2B4 C/BE[7]# GND C/BE[6]#
3 RSV GND RSV RSV RSV
2 RSV RSV SYSEN#
a
RSV RSV
1 RSV GND RSV RSV RSV
a. Defined as SYSEN#. This OV allows the CPCI-6115 to ensure that it is installed into a peripheral slot.
Table 3-5 CompactPCI Connector, J2 (continued)
Pin Row A Row B Row C Row D Row E
Table 3-6 User I/O Connector Pinout, J3
Pin Row A Row B Row C Row D Row E Pin
19 GND +12 V -12 V GND GND 19
18 LPa_DA+ (TX1+) LPa_DA- (TX1-) GND LPa_DC+ LPa_DC- 18
17 LPa_DB+ (RX1+) LPa_DB- (RX1-) GND LPa_DD+ LPa_DD- 17
16 LPb_DA+ (TX2+) LPb_DA- (TX1-) GND LPb_DC+ LPb_DC- 16
15 LPb_DB+ (RX2+) LPb_DB- (RX2-) GND LPb_DD+ LPb_DD- 15
- CPCI-6115 CompactPCI 1
- Single Board Computer 1
- Trademarks 2
- Contents 3
- List of Tables 10
- List of Figures 11
- About this Manual 13
- Abbreviations 14
- Conventions 16
- Summary of Changes 17
- Comments and Suggestions 18
- Safety Notes 19
- Operation 20
- Installation 20
- Cabling and Connectors 21
- Environment 22
- Sicherheitshinweise 23
- Schaltereinstellungen/Jumper 24
- Kabel und Stecker 26
- Umweltschutz 26
- Batterie 26
- Introduction 27
- 1.2 Standard Compliances 28
- 1.3 Ordering Information 29
- 2.1 Overview 31
- Requirements 32
- 2.3.2 Power Requirements 34
- 2.3.3 Thermal Requirements 34
- 2.4 Getting Started 37
- 2.5 Baseboard Preparation 38
- 2.5.3 J6, Bus Mode Selection 40
- 2.5.7 J20, Safe Start Header 42
- 2.6 Operating Modes 44
- 2.7 Installing Hardware 44
- Procedure 45
- Personal Injury or Death 46
- 2.9 Applying Power 49
- 3.1 Overview 51
- 3.2 Board Layout 52
- 3.4 ABORT/Reset Switch 54
- 3.5.7 CompactPCI Connector 58
- PCI_RSVD = PCI Reserved pin 62
- 3.5.14 Safe Start Header 67
- 3.5.15 Bus Mode Select Header 67
- 3.5.18 +/-12 V Present Header 68
- Functional Description 69
- 4.2 Block Diagram 70
- 4.3 General Description 71
- 4.3.2 Processor 72
- 4.3.3 L3 Cache 72
- 4.3.4.12 Interrupt Controller 76
- 4.3.4.13 PCI Bus Arbitration 76
- 4.3.4.14 Board Reset Logic 77
- 4.3.5 System Memory 81
- 4.3.6 Flash Memory 82
- 4.3.8 TL16C550C UART Devices 83
- 4.3.9 System Registers 83
- 4.3.10 Serial EEPROM Devices 83
- 4.3.11 PCI Bus 0.0 83
- 4.3.12 PCI Bus 1.0 83
- 4.3.13 IDE Controller 84
- 4.3.15 CompactPCI Bus 84
- 4.3.16 PMC Slots 84
- 4.4 Miscellaneous 86
- 4.4.3 Onboard Power Supplies 89
- 4.4.4 Hot Swap Support 89
- 4.4.5 Hot Swap Process 89
- 5.2 Block Diagram 92
- 5.4 Rear Panel Connectors 94
- 5.5.2.1 Host IO Connectors 96
- 5.5.2.2 PMC I/O Connectors 98
- 5.6 Jumper Settings 104
- 5.7 Functional Description 105
- 5.7.3 Hot-Swap Support 106
- 5.7.4 Serial EEPROM 106
- 5.7.5 PMC I/O Modules 106
- 5.7.7 PMC I/O Module 110
- 5.7.9 PMC I/O Connector 112
- 5.7.10 Host I/O Connector 112
- 5.8 Installing the PIM 113
- Figure 5-9 Installing the PIM 114
- Remote Start via the PCI Bus 117
- MOTLoad Firmware 119
- 7.4 MOTLoad Commands 120
- 7.6 MOTLoad Tests 120
- 7.7 Using MOTLoad 121
- 7.7.2 Command Line Help 122
- 7.7.3 Command Line Rules 122
- 7.8 MOTLoad Command List 123
- Memory Maps 127
- 8.2.2 Processor Memory Map 128
- 8.2.3 Default PCI Memory Map 129
- 8.2.5 System I/O Memory Map 131
- 8.2.7 CompactPCI Memory Map 131
- 8.2.9 L1, L2 and L3 Cache 132
- 8.2.10 System Memory 132
- A Related Documentation 133
- A.3 Related Specifications 134
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