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CompactPCI User I/O Connector Controls, LEDs, and Connectors
CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)
57
3.5.8 CompactPCI User I/O Connector
Connector J5 is a 110-pin AMP Z-pack 2mm hard metric type B connector. This connector
routes the I/O signals for one PMC site, an IDE channel, two asynchronous serial ports and the
I2C clock and data signals to the CompactPCI backplane. The pin assignments for J5 are as
follows: (Note that outer row F is assigned and used as ground pins but is not shown in the
table).
Table 3-7 User I/O Connector Pinout, J5
PinRow ARow BRow CRow DRow EPin
22 DRESET# NC NC COM2_TXD COM1_TXD 22
21 INTRQ NC NC COM2_RXD COM1_RXD 21
20 CS1FX# (CS0) CS3FX# (CS1) DA2 MXDI MXDO 20
19 DMACK# DIORDY DA1 MXCLK MXSYNC# 19
18 DIOW# DA0 TMCOM1# I2C_CLK I2C_DATA 18
17GND DD14DD15DIOR#DMARQ17
16 DD9 DD10 DD11 DD12 DD13 16
15 DD5 DD6 GND DD7 DD8 15
14 DD0 DD1 DD2 DD3 DD4 14
13 PMCIO5 PMCIO4 PMCIO3 PMCIO2 PMCIO1 13
12PMCIO10PMCIO9PMCIO8PMCIO7PMCIO612
11 PMCIO15 PMCIO14 PMCIO13 PMCIO12 PMCIO11 11
10 PMCIO20 PMCIO19 PMCIO18 PMCIO17 PMCIO16 10
9 PMCIO25 PMCIO24 PMCIO23 PMCIO22 PMCIO21 9
8 PMCIO30 PMCIO29 PMCIO28 PMCIO27 PMCIO26 8
7 PMCIO35 PMCIO34 PMCIO33 PMCIO32 PMCIO31 7
6 PMCIO40 PMCIO39 PMCIO38 PMCIO37 PMCIO36 6
5 PMCIO45 PMCIO44 PMCIO43 PMCIO42 PMCIO41 5
4 PMCIO50 PMCIO49 PMCIO48 PMCIO47 PMCIO46 4
3 PMCIO55 PMCIO54 PMCIO53 PMCIO52 PMCIO51 3
2 PMCIO60 PMCIO59 PMCIO58 PMCIO57 PMCIO56 2
1 TM_PRSNT# PMCIO64 PMCIO63 PMCIO62 PMCIO61 1
Signal Descriptions
IDE Port, TTL Levels:
DMARQ DMA request
DMACK_L DMA acknowledge
DIOR_L I/O read
- CPCI-6115 CompactPCI 1
- Single Board Computer 1
- Trademarks 2
- Contents 3
- List of Tables 10
- List of Figures 11
- About this Manual 13
- Abbreviations 14
- Conventions 16
- Summary of Changes 17
- Comments and Suggestions 18
- Safety Notes 19
- Operation 20
- Installation 20
- Cabling and Connectors 21
- Environment 22
- Sicherheitshinweise 23
- Schaltereinstellungen/Jumper 24
- Kabel und Stecker 26
- Umweltschutz 26
- Batterie 26
- Introduction 27
- 1.2 Standard Compliances 28
- 1.3 Ordering Information 29
- 2.1 Overview 31
- Requirements 32
- 2.3.2 Power Requirements 34
- 2.3.3 Thermal Requirements 34
- 2.4 Getting Started 37
- 2.5 Baseboard Preparation 38
- 2.5.3 J6, Bus Mode Selection 40
- 2.5.7 J20, Safe Start Header 42
- 2.6 Operating Modes 44
- 2.7 Installing Hardware 44
- Procedure 45
- Personal Injury or Death 46
- 2.9 Applying Power 49
- 3.1 Overview 51
- 3.2 Board Layout 52
- 3.4 ABORT/Reset Switch 54
- 3.5.7 CompactPCI Connector 58
- PCI_RSVD = PCI Reserved pin 62
- 3.5.14 Safe Start Header 67
- 3.5.15 Bus Mode Select Header 67
- 3.5.18 +/-12 V Present Header 68
- Functional Description 69
- 4.2 Block Diagram 70
- 4.3 General Description 71
- 4.3.2 Processor 72
- 4.3.3 L3 Cache 72
- 4.3.4.12 Interrupt Controller 76
- 4.3.4.13 PCI Bus Arbitration 76
- 4.3.4.14 Board Reset Logic 77
- 4.3.5 System Memory 81
- 4.3.6 Flash Memory 82
- 4.3.8 TL16C550C UART Devices 83
- 4.3.9 System Registers 83
- 4.3.10 Serial EEPROM Devices 83
- 4.3.11 PCI Bus 0.0 83
- 4.3.12 PCI Bus 1.0 83
- 4.3.13 IDE Controller 84
- 4.3.15 CompactPCI Bus 84
- 4.3.16 PMC Slots 84
- 4.4 Miscellaneous 86
- 4.4.3 Onboard Power Supplies 89
- 4.4.4 Hot Swap Support 89
- 4.4.5 Hot Swap Process 89
- 5.2 Block Diagram 92
- 5.4 Rear Panel Connectors 94
- 5.5.2.1 Host IO Connectors 96
- 5.5.2.2 PMC I/O Connectors 98
- 5.6 Jumper Settings 104
- 5.7 Functional Description 105
- 5.7.3 Hot-Swap Support 106
- 5.7.4 Serial EEPROM 106
- 5.7.5 PMC I/O Modules 106
- 5.7.7 PMC I/O Module 110
- 5.7.9 PMC I/O Connector 112
- 5.7.10 Host I/O Connector 112
- 5.8 Installing the PIM 113
- Figure 5-9 Installing the PIM 114
- Remote Start via the PCI Bus 117
- MOTLoad Firmware 119
- 7.4 MOTLoad Commands 120
- 7.6 MOTLoad Tests 120
- 7.7 Using MOTLoad 121
- 7.7.2 Command Line Help 122
- 7.7.3 Command Line Rules 122
- 7.8 MOTLoad Command List 123
- Memory Maps 127
- 8.2.2 Processor Memory Map 128
- 8.2.3 Default PCI Memory Map 129
- 8.2.5 System I/O Memory Map 131
- 8.2.7 CompactPCI Memory Map 131
- 8.2.9 L1, L2 and L3 Cache 132
- 8.2.10 System Memory 132
- A Related Documentation 133
- A.3 Related Specifications 134
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