Motorola MVME2300 Series User Manual Page 75
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Functional Description
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2
Figure 2-2. MPC-to-PCI Address Decoding
The Raven ASIC imposes no limits on how large an address space a map
decoder can represent. There is a minimum of 64KB due to the resolution
of the address compare logic.
For each map, there is an associated set of attributes. These attributes are
used to enable read accesses, enable write accesses, enable write-posting,
and define the PCI transfer characteristics.
Each map decoder also includes a programmable 16-bit address offset. The
offset is added to the 16 most significant bits of the MPC address, and the
result is used as the PCI address. This offset allows PCI devices to reside
at any PCI address, independent of the MPC address map. An example of
this appears in Figure 2-3.
MPC Bus Address
8
0801234
31
16150
MSADDx Register
7
0809000
31
1615 0
>= <=andDecode is
- Programmer’s Reference 1
- Safety Summary 3
- Flammability 4
- EMI Caution 4
- Lithium Battery Caution 4
- Contents 7
- List of Figures 15
- List of Tables 17
- About This Manual 19
- Summary of Changes 20
- Overview of Contents 21
- Comments and Suggestions 21
- 1Board Description and Memory 25
- Summary of Features 26
- System Block Diagram 27
- PCI Memory Maps 37
- Configuration 39
- VMEbus Mapping 44
- PCI Memory 46
- Processor 46
- ISA Space 46
- PCI I/O Space 46
- System External Cache 48
- Control Register 48
- CPU Control Register 48
- SYSXC P0STAT P1STAT 49
- ISA Local Resource Bus 55
- 0s (jumpers on 56
- VME Registers 61
- Z8536 CIO Port Pins 68
- PCI devices to reside 75
- PCI Interface 80
- ❏ Memory and I/O 91
- ❏ Configuration 91
- ❏ Special Cycle 91
- ❏ Interrupt Acknowledge 91
- Endian Conversion 95
- Error Handling 98
- Transaction Ordering 99
- Raven Registers 100
- Raven PCI Bridge ASIC 108
- Attribute (3) Registers 114
- PCI Registers 117
- PSADD0 - $80 124
- 0,1,2 and 3) Registers 125
- PSATT0/PSOFF0 - $84 125
- $CF8 $CF9 $CFA $CFB 126
- $CFB $CFA $CF9 $CF8 126
- $CFC $CFD $CFE $CFF 127
- 2Raven PCI Bridge ASIC 128
- 0Raven Registers 128
- $CFF $CFE $CFD $CFC 129
- Raven Interrupt Controller 130
- Block Diagram Description 135
- MPIC Registers 139
- IPI 0 - $010A0 146
- Timer 0 - $01100 148
- Timer 0 - $01110 148
- Timer 0 - $01120 149
- Timer 0 - $01130 150
- Int Src 0 - $10000 151
- Int Src 0 - $10010 152
- Processor 0 $20080 155
- Processor 0 $200A0 156
- Processor 0 $200B0 156
- Programming Notes 157
- Architectural Notes 161
- 3Falcon ECC Memory Controller 163
- Chip Set 163
- Block Diagrams 164
- 1902 9609 166
- Functional Description 167
- PowerPC 60 173
- Bus Interface 173
- ×[64+8]) 174
- DRAM Tester 176
- ROM/Flash Interface 176
- Table 3-8. PowerPC 60 178
- Table 3-9. PowerPC 60 179
- Refresh/Scrub 180
- DRAM Arbitration 182
- Chip Defaults 182
- Programming Model 183
- Upper FALCON 184
- Lower FALCON 184
- MPC60x Master 184
- 1905 9609 186
- 1907 9609 188
- 1908 9609 188
- Register Summary 189
- Table 3-10. Register Summary 190
- EXTERNAL REGISTER SET 192
- READ/WRITE 212
- Software Considerations 215
- Sizing DRAM 216
- Table 3-18. Sizing Addresses 218
- Table 3-19. PowerPC 60 218
- ECC Codes 219
- Data Paths 222
- Introduction 225
- Features 225
- Block Diagram 227
- VMEbus Interface 228
- PCI Bus Interface 229
- Interrupter 230
- DMA Controller 231
- Universe (VMEbus to PCI) Chip 232
- Universe Register Map 233
- Register Name 234
- LSI0_TO 234
- LSI1_TO 235
- LSI2_TO 235
- LSI3_TO 235
- Examples 240
- 5Programming Details 245
- Programming Details 246
- RavenMPIC 247
- 8259 Interrupts 248
- Interrupt Handling 249
- ISA DMA Channels 251
- Exceptions 252
- Soft Reset 253
- Endian Issues 255
- PCI Local Bus 255
- 60X System Bus 255
- Processor/Memory Domain 257
- Role of the Raven ASIC 257
- PCI Domain 257
- Role of the Universe ASIC 258
- VMEbus Domain 258
- ROM/Flash Initialization 259
- ARelated Documentation 261
- Manufacturers’ Documents 262
- Related Specifications 264
- Glossary 267
- Numerics 275
- 1 and 2) 280
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