Motorola MVME2300 Series User Manual Page 130

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2-60 Computer Group Literature Center Web Site
Raven PCI Bridge ASIC
2
Raven Interrupt Controller
This section describes the general implementation of the Raven Interrupt
Controller (RavenMPIC).
Features
The RavenMPIC has the characteristics listed below.
MPIC programming model
Support for two processors
Support for 16 external interrupts
Support for 15 programmable Interrupt and Processor Task priority
levels
Support for the connection of an external 8259 for ISA/AT
compatibility
Distributed interrupt delivery for external I/O interrupts
Direct/Multicast interrupt delivery for Interprocessor and timer
interrupts
Four Interprocessor Interrupt sources
Four timers
Processor initialization control
Architecture
The Raven PCI Slave implements two address decoders for placing the
RavenMPIC registers in PCI IO or PCI Memory space. Access to these
registers require MPC and PCI bus mastership. These accesses include
interrupt and timer initialization and interrupt vector reads.
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