Motorola MVME2300 Series User Manual download pdf (Page 216)

3-54 Computer Group Literature Center Web Site

Falcon ECC Memory Controller Chip Set

As with DRAM, software should not change control register bits that affect

ROM/Flash while the affected block is being accessed. This generally

means that the ROM/Flash size, base address, enable, write enable, etc. are

changed only during initial execution in the reset vector area ($FFF00000

- $FFFFFFFF).

Sizing DRAM

Caution

To satisfy DRAM component requirements before the memory is used at

start-up, software must always wait at least 500

s after the initial setting

of a bank’s size bits to a nonzero value before the initial access to that

bank. These settings are stored in the DRAM Attributes register (offset

$FEF80010). The delay is introduced to ensure that the bank has been

refreshed at least eight times before use. The 500

s interval is sufficient,

as the CLK Frequency register (offset $FEF80020) is within a factor of

two of matching the actual processor clock frequency.

The following routine can be used to size DRAM for the Falcon.

First, initialize the Falcon control register bits to a known state as follows:

1. Clear the isa_hole bit.

2. Make sure that ram_fref and ram_spd0,ram_spd1 are correct.

3. Set CLK_FREQUENCY to match the operating frequency.

4. Clear the refdis, rwcb bits.

5. Set the derc bit.

6. Clear the scien, tien, sien, and mien bits.

7. Clear the mcken bit.

8. Clear the swen and rtest0,rtest1,rtest2 bits.

9. Make sure that ROM/Flash banks A and B are not enabled to

respond in the range from $00000000 to $40000000.

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Motorola MVME2300 Series User Manual Page 216