Motorola ColdFire MCF5282 User Manual Page 20
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1-8 M5282EVB User’s Manual
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Support Logic
1.2.6.2 Reset Vector Mapping
Asserting the reset input signal to the processor causes a reset exception. The reset exception has
the highest priority of any exception; it provides for system initialization and recovery from
catastrophic failure. Reset also aborts any processing in progress when the reset input is
recognized. Processing cannot be recovered.
The reset exception places the processor in the supervisor mode by setting the S-bit and disables
tracing by clearing the T bit in the SR. This exception also clears the M-bit and sets the processor’s
interrupt priority mask in the SR to the highest level (level 7). Next, the VBR is initialized to zero
(0x00000000). The control registers specifying the operation of any memories (e.g., cache and/or
RAM modules) connected directly to the processor are disabled.
Once the processor is granted the bus, it then performs two longword read bus cycles. The first
longword at address 0 is loaded into the stack pointer and the second longword at address 4 is
loaded into the program counter. After the initial instruction is fetched from memory, program
execution begins at the address in the PC. If an access error or address error occurs before the first
instruction is executed, the processor enters the fault-on-fault halted state.
The Memory that the MCF5282 accesses at address 0 is determined at reset by sampling D[19:18].
1.3 Support Logic
1.3.1 Reset Logic
The reset logic provides system initialization. Reset occurs during power-on or via assertion of the
signal RESET
which causes the MCF5282 to reset. RSTI is triggered by the reset switch (SW2)
which resets the entire processor/system.
dBUG configures the MCF5282 microprocessor internal resources during initialization. The
contents of the exception table are copied to address 0x0000_0000 in the SDRAM. The Software
Table 1-2. JP 6 - CS0 Settings
JP6 CS0 CS1
Across 1&2, 3&4 External Flash External SRAM
Across 1&3, 2&4 External SRAM External Flash
Table 1-3. D[19:18] External Boot Chip Select Configuration
D[19:18]
Boot Device/Data Port
Size
00
Internal (32-bit)
01
External (16-bit)
10
External (8-bit)
11
External (32-bit)
- M5282EVB User's Manual 1
- Contents 5
- MOTOROLA Tables v 9
- ILLUSTRATIONS 11
- Chapter 1 13
- 1-2 M5282EVB User’s Manual 14
- 1.1 MCF5282 Microprocessor 15
- 1-4 M5282EVB User’s Manual 16
- MCF5282 Microprocessor 16
- Chapter 1. M5282EVB 1-5 17
- 1.2 System Memory 18
- 1.2.6 M5282EVB Memory Map 19
- 1.3 Support Logic 20
- Chapter 1. M5282EVB 1-9 21
- Support Logic 21
- 1.3.2 Clock Circuitry 22
- 1.3.3 Watchdog Timer 22
- 1.3.4 Exception Sources 23
- 1.3.5 TA Generation 23
- 1.4 Communication Ports 24
- 1.4.2 FlexCAN 2.0 B Port 25
- 1.4.3 10/100T Ethernet Port 26
- 1.4.4 BDM/JTAG Port 26
- 1.4.5 I 27
- 1.4.6 QSPI 28
- 1.5.1 Expansion Connectors 28
- Table 1-18. J6 29
- Table 1-19. J7 29
- Table 1-17. J5 29
- Table 1-20. J2 30
- 1.5.3 Reset Switch (S2) 31
- 1.5.4 User LEDs 32
- 1.5.5 Other LEDs 32
- 1.7 Software Development 33
- 1-22 M5282EVB User’s Manual 34
- Software Development 34
- 2.1 System Configuration 35
- 6 - 12 V 36
- Input Power 36
- RS-232 Terminal 36
- 2.2 Installation and Setup 37
- 2-4 M5282EVB User’s Manual 38
- Installation and Setup 38
- Figure 2-3. Jumper Locations 40
- 2.4 Using The BDM Port 41
- 2-8 M5282EVB User’s Manual 42
- Using The BDM Port 42
- Chapter 3 43
- 3.2 Operational Procedure 44
- 3.2.2 System Initialization 45
- 3.3 Command Line Usage 46
- 3.4 Commands 47
- 3-6 M5282EVB User’s Manual 48
- Commands 48
- ASM Assembler 49
- BC Block Compare 50
- BF Block Fill 51
- BM Block Move 52
- BR Breakpoints 53
- BS Block Search 54
- DC Data Conversion 55
- DI Disassemble 56
- DL Download Console 57
- DN Download Network 58
- GO Execute 59
- GT Execute To 60
- IRD Internal Register Display 61
- IRM Internal Register Modify 62
- HELP Help 63
- LR Loop Read 64
- LW Loop Write 65
- MD Memory Display 66
- MM Memory Modify 67
- MMAP Memory Map Display 68
- RD Register Display 69
- RM Register Modify 70
- SET Set Configurations 72
- SHOW Show Configurations 73
- STEP Step Over 74
- SYMBOL Symbol Name Management 75
- TRACE Trace Into 76
- UPDBUG Update dBUG 77
- UPUSER Update User Flash 78
- 3.5 TRAP #15 Functions 79
- 3.5.2 IN_CHAR 80
- 3.5.3 CHAR_PRESENT 80
- 3.5.4 EXIT_TO_dBUG 81
- 3-40 M5282EVB User’s Manual 82
- TRAP #15 Functions 82
- Appendix A 83
- Configuring dBUG for Network 83
- Downloads 83
- Appendix B 87
- Schematics 87
- Fire®Cold MCF5282 88
- Evaluation Board - M5282EVB 88
- CAN Bus Connector 89
- - 9 way D-type (Female) 89
- Cold Fire® 90
- SDRAM Upper 16-bit Word 99
- SDRAM Lower 16-bit Word 99
- RS232 Transceiver 100
- NOT POPULATED AT ASSEMBLY 100
- Appendix C 101
- Evaluation Board BOM 101
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