Motorola MPC8260 User Manual download pdf (Page 9)

MOTOROLA

MPC8260 PowerQUICC II

to CAM Interfacing – MCM69C433

MPC8260 Register Programming

After the start-up functions are completed, the CAM table can be loaded. Each 64-bit data entry is

constructed by writing a 16-bit value into each of the four I/O registers and issuing the INSERT VALUE

command. After the INITIALIZE TABLE command is executed (if required), normal matching can begin.

The DELETE VALUE command can be used to remove data from the CAM table.

The ﬂag register gives the status of various states of operation. If an error occurs, one of several error codes

appears in the error code register. Although in this document the CAM interrupt (IRQ

) signal is not used,

several conditions can be programmed into the interrupt register to assert the CAM IRQ

signal.

4.5 Transaction Timing Diagrams

Figures 2 through 5 below are timing diagrams of the 8260/CAM interface at 66 MHz. Results were derived

via Verilog simulation of the MPC8260 SWIFT Model - Solaris: Rev. B.0 Bus Function Model (available

on Motorola’s MPC8260 Product Summary website) and the MPC69C433 HDL CAM model. Write and

read transaction via the CAM control and match port are shown.

Figure 2. PowerQUICC II

Write Cycle (CAM Control Port Read)

sp30

sp30+3.75

sp30sp35

sp30

sp30sp30sp30

sp30

sp30+3.75

sp30

sp35+3.75

sp30sp32

tWVSL

tDVSLtDVSL

tAVSL

8260 Write to CAM Control Port

0ns 100ns 200ns 300ns

CLK

8260 ADDR/CAM A2-A0

8260 CS[1]/CAM SELB

8260 LOCAL DATA/CAM DQ[15:0]

8260 LWR/CAM WEB

Frees

cale Semiconductor,

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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