Motorola MPC8260 User Manual download pdf (Page 2)

MPC8260 PowerQUICC II

to CAM Interfacing – MCM69C433

MOTOROLA

CAM Interface CAM Interface

3 CAM Interface

The CAM consists of two independent ports: the control port and the match port. They have different

functionality and control requirements. The MPC8260 local bus asserts one unique chip select for control

port access and another for the match port. Because the MPC8260 is only able to assert one chip select per

memory bank access, the MPC8260 accesses one CAM port at a time; the CAM control port and match port

cannot be selected simultaneously. Also note on the MPC8260, some functions are multiplexed with other

functions on the same pins. Particularly, on some pins, there are SDRAM signals that reside with signals

that are used in the MPC8260/CAM interface. Therefore for this interface, SDRAM cannot be used on the

local bus along with the CAM.

3.1 Control Port Interfacing Using the MPC8260 GPCM

The CAM control port is an asynchronous 16-bit read/write port. The control port signals consist of A2-A0

(Address), SEL

(Select), IRQ (Interrupt), DTACK (Data Acknowledgement), WE (Write Enable), and

RESET

The MPC8260 can reset the CAM in software, as the RESET

input of the CAM is driven by the hardware

reset of the MPC8260. For write transactions, the CAM address and data value should be valid, and the WE

should be low when the SEL signal is asserted to begin a write cycle. Address, WE, and SEL signal values

should be held until the CAM asserts the DT

ACK signal to end the write cycle. Note however, that DTACK

will not be used in this application and is pulled up with a 1k

Ω

resistor. The MPC8260 has an internal signal

that will end the write transaction. See the Option Register setting in section 4.1 for further details. For read

transactions, the address value should be valid and the WE

signal should be high when SEL is asserted. Both

signals (address, WE

, and SEL) should hold their values until the CAM asserts the DTACK signal to end

the read cycle. Again, as in the likewise manner of the write sequence, DT

ACK will not be used to end the

read transaction.

This memory controller chip behavior can be accomplished via the MPC8260 Memory Controller’s

General Purpose Chip Select Machine (GPCM). The GPCM allows ﬂexible interfacing between the

MPC8260, SRAM, EPROM, ﬂash EPROM, ROM devices and external peripherals. The table below lists

the interface signals of the GPCM.

From the table, GPCM signals can be generated either on the 60x bus or the local bus. For this document,

the MPC8260/CAM control port interfacing will take place on the local bus. The Write enable (L

WE[0-3])

and the Transaction Termination signal (L

GTA) will not be used.

A device select from the MPC8260, CS

[1], functions as the CAM SEL while the LWR acts as the CAM

. The control port is only accessible through 16-bit accesses. Therefore, the CAM address lines A[2:0]

will map to the MPC8260 address lines A[28:30] (Each byte of data within the MPC8260 addressing

Table 1. GPCM Interface Signals

60x Bus Local Bus Comments

[0-11] Device Select

WE [0–7] LWE [0–3] Write enables for write cycles

LOE Output enables for read cycles

PGTA LGTA Transaction Termination

BCTLx LWR Data Buffer Controls/Local

Write-Read

Frees

cale Semiconductor,

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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