Motorola MPC8260 User Manual download pdf (Page 3)

MOTOROLA

MPC8260 PowerQUICC II

to CAM Interfacing – MCM69C433

CAM Interface

scheme has a unique address. Since data transactions will occur on 16-bit intervals [two bytes], A[31] of the

MPC8260 address will not be used). The CAM control port data bus (DQ[15:0]) will connect to the

MPC8260’s local data bus LCL_D[0-15]. The CAM also includes the IRQ

signal that can optionally alert

the user of certain conditions within the CAM. For this demonstration, IRQ

is not used and is pulled up by

means of a 1k

Ω

resistor.

3.2 Match Port Interfacing Using the MPC8260 UPM

The CAM match port is synchronous to the input clock (K). The match port is 32 bits wide with read/write

capability. Accesses to the match port from the MPC8260 consist of a write transaction followed by a read.

The write cycle drives match data into the CAM. This data is latched in when the CAM LH/SM

(Latch

High/Start Match) signal asserts. The completion of a match search is indicated with the CAM MC

(Match

Complete) asserting. If a match is found, MS

(Match Successful) asserts. The MPC8260 performs a read

cycle with data being driven by the CAM with the CAM output enable, G

The MPC8260 Memory Controller’s User-Programmable Machine (UPM) will be mapped to the match port

of the CAM. The UPM provides ﬂexible interfaces to a wide array of memory devices. The heart of the UPM

is the programmable internal-memory RAM array. Each 64-bit word, which is programmed by the user,

speciﬁes the signal values for a given clock cycle that are driven on the external memory pins. The table

below lists the interface signals of the UPM:

From Table 2, UPM signals can be generated either on the 60x bus or the local bus. For this document, the

MPC8260/CAM match port interfacing will take place on the local bus.

The UPM’s CS

[2] and LGPL[5] signals are mapped to the CAM LH/SM and G signals, respectively. The

UPM will be programmed to assert CS

[2] (LH/SM) during write cycles and LGPL[5] (G) during read

cycles. The CAM MC

signal (pulled up through a 1k

Ω

resistor) is mapped to the UPM LGPL_4/UPWAIT

pin. During a write cycle on the CAM match port, MC

deasserts and goes into a high state. This in turn,

asserts the UPM UPWAIT signal (this is an active high signal). When UPWAIT is active, the current

transaction is frozen until UPWAIT is deasserted (a low state); this occurs when the match algorithm

completes and MC

enters a low state. All match data written from the MPC8260 will be 32-bit operands; all

return data from the CAM will be 32-bit operands. Thereby, the byte select signals (LBS[x]) will not be

used. For applications such as Ethernet or ATM, the MPC8260 requires an indication if a match attempt was

either successful or not successful. The MPC8260 checks the msb (LCL_D[0]) of the returned data. If the

bit is cleared, the data is accepted. If the bit is set, the data is rejected. Therefore, the CAM MS

signal (pulled

high) will accommodate this requirement. The CAM LL

(latch low) signal is needed if the match data

Table 2.

UPM Interface Signals

60x Bus Local Bus Comments

[0-11] Device select

PBS[0–7] LBS[0–3] Byte select

PGPL_0 LGPL_0 General-purpose line 0

PGPL_1 LGPL_1 General-purpose line 1

PGPL_2 LGPL_2 General-purpose line 2

PGPL_3 LGPL_3 General-purpose line 3

PGPL_4/UPWAIT LGPL_4/UPWAIT General-purpose line 4/UPM WAIT

PGPL_5 LGPL_5 General-purpose line 5

Frees

cale Semiconductor,

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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