Motorola MPC8260 User Manual download pdf (Page 4)

MPC8260 PowerQUICC II

to CAM Interfacing – MCM69C433

MOTOROLA

MPC8260 Register Programming MPC8260 Register Programming

written to the CAM requires more than one 32-bit write transaction (for example, if the input match data

were 48 bits wide, LL

would latch in the lower 16 bits; then, LHSM would latch in the higher 32 bits). For

purposes of this document, LL

is pulled high and not used. The 32-bit CAM data bus, MQ[31:0], is mapped

to the MPC8260 local data bus, LCL_D[0-31].

Figure 1 below gives an illustration of the MPC8260/CAM interface:

Figure 1. MPC8260/CAM

4 MPC8260 Register Programming

In order to utilize the MPC8260’s GPCM and the UPM, two registers in the MPC8260 must be

programmed: the base register and the option register. The base registers (BR0-BR11) hold information

such as the base address of the memory peripheral (the CAM), the memory attributes, and the selection of

the machine handling the memory accesses. The option registers (OP0-OP11) deﬁne the size of the memory

banks and other access attributes that are depending on the machine selected.

MPC8260

PowerQUICC II™

See note

Clock source @ 66 MHz

MCM69C433

CAM

Note: Assert KMODE 1 clock cycle after RESET is deasserted.

Local address[28:30]

SIU/Memory

controller GPCM

CS1

Local data bus[0:15]

Local wr

ite enable

HRESET

SIU/Memory

controller UPM

UPWAIT

CS2

CLK

LGPL5

Local data bit 0

Local data bus[1:31]

Control port

A[2:0]

SEL

DQ[15:0]

IRQ

RESET

KMODE

DTACKB

Match port

LH/SM

MQ31

MQ[30:0]

Frees

cale Semiconductor,

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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