Motorola M68CPU32BUG User Manual download pdf (Page 63)

SUPPORT INFORMATION

M68332BCC/D 5-7 MOTOROLA

REV 1

Table 5-3. J8 Background Mode Connector Pin Assignments

Pin Number

Signal Mnemonic

Signal Name And Description

DATA STROBE – Active-low output signal, that during

a read cycle, indicates that an external device should

place valid data on the data bus. During the write cycle,

DS indicates that valid data is on the data bus.

BERR

BUS ERROR – Active-low input signal that indicates

that an erroneous bus operation is being attempted.

3 GND GROUND

BKPT

DSCLK

BREAKPOINT – An active-low input signal that places

the CPU32 in background debug mode.

DEVELOPMENT SYSTEM CLOCK – Serial input clock

for background debug mode.

5 GND GROUND

6 FREEZE /

QUOT

FREEZE – Output signal that indicates that the CPU32

has entered background debug mode.

QUOTIENT OUT – Output signal that furnishes the

quotient bit of the polynomial divider for test purposes

RESET

RESET – Active-low input/output signal for initiating a

system reset.

IFETCH

DSI

INSTRUCTION FETCH – Active-low output signal that

indicates when the CPU is performing an instruction

word pre-fetch and when the instruction pipeline has

been flushed.

DEVELOPMENT SERIAL IN – Serial data input for

background debug mode.

9 +5V +5 VOLT INPUT POWER

IPIPE

DSO

INSTRUCTION PIPE – Active-low output signal used to

track movement of words through the instruction

pipeline.

DEVELOPMENT SERIAL OUT – Serial output for

background debug mode.

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Motorola M68CPU32BUG User Manual Page 63

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