Motorola M68CPU32BUG User Manual download pdf (Page 59)

SUPPORT INFORMATION

M68332BCC/D 5-3 MOTOROLA

REV 1

Table 5-1. P1 Expansion Connector Pin Assignments (continued)

Pin Number

Signal Mnemonic

Signal Name And Description

BKPT

DSCLK

BREAKPOINT – An active-low input signal that places

the CPU32 in background debug mode.

DEVELOPMENT SYSTEM CLOCK – Serial input clock

for background debug mode.

56 RXD RECEIVE DATA – Serial data input line.

RESET

RESET – Active-low input/output signal for initiating a

system reset.

58 FREEZE /

QUOT

FREEZE – Output signal that indicates that the CPU32

has entered background debug mode.

QUOTIENT OUT – Output signal that furnishes the

quotient bit of the polynomial divider for test purposes.

IPIPE

DSO

INSTRUCTION PIPE – Active-low output signal used to

track movement of words through the instruction

pipeline.

DEVELOPMENT SERIAL OUT – Serial output for

background debug mode.

IFETCH

DSI

INSTRUCTION FETCH – Active-low output signal that

indicates when the CPU is performing an instruction

word pre-fetch and when the instruction pipeline has

been flushed.

DEVELOPMENT SERIAL IN – Serial data input for

background debug mode.

61, 62 +5V +5 VOLT INPUT POWER

63, 64 GND GROUND

1 2 ... 54 55 56 57 58 59 60 61 62 63 64 ... 67 68

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Motorola M68CPU32BUG User Manual Page 59