Motorola M68CPU32BUG User Manual Page 30

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OPERATING INSTRUCTIONS
M68332BCC/D 3-2 MOTOROLA
REV 1
3.2.1 Chip Select Usage
The MC68332 MCU has chip select signals that enable peripheral devices. The BCC requires
some of these chip selects for BCC operation making them unavailable to the user. Do not
remove the chip selects used by the BCC, or CPU32Bug will not operate. In addition to the chip
selects employed on the BCC, other chip selects are used elsewhere in the M68332EVK (refer to
Tables 3-1 through 3-3).
Depending on the user’s environment, any or all of the chip selects may be re-configured for an
alternate function (i.e., as I/O or address lines). Chip select pins used by the BCC and EVK
cannot be used in their alternate capacities.
Although a chip select (CS8 on Rev. A and CS4 on Rev. B and Rev. C BCCs) is dedicated for
the ABORT switch, the pin is not used. Instead the chip select decodes the interrupt acknowledge
(IACK) cycle in response to a level 7 interrupt generated by the ABORT switch. Refer the
System Integration Module User’s Manual (SIM32UM/AD) for more information.
When the BCC is not mounted on the M68300PFB Platform Board (PFB), these chip selects are
available to the user. Also if the PFB RAM/EPROM socket pairs (U1/U3, U2/U4) and
coprocessor socket U5 are not populated, the chip selects are available to the user.
Table 3-1. BCC Rev. A Chip Selection Summary
Signal Board/Chip Description Memory Type
CSBOOT BCC U2 CPU32Bug EPROM
CS0 BCC U1 read/write enable for MSB=UPPER=EVEN RAM
CS1 BCC U3 read/write enable for LSB=LOWER=ODD RAM
CS2 PFB U1/U3 read enable for MSB/LSB=BOTH RAM
CS3 PFB U1 write enable for LSB=LOWER=ODD RAM
CS4 PFB U4 read enable for MSB=UPPER=EVEN RAM/EPROM
CS5 PFB U2 read enable for LSB=LOWER=ODD RAM/EPROM
CS6 PFB U5 chip enable for MC68881/882
CS7 <unused>
CS8 PFB ABORT push-button autovector
CS9 <unused>
CS10 PFB U3 write enable for MSB=UPPER=EVEN
cut/jump U3-27 from CS4 to CS10 required.
RAM
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