Motorola M68CPU32BUG User Manual download pdf (Page 61)

SUPPORT INFORMATION

M68332BCC/D 5-5 MOTOROLA

REV 1

Table 5-2. P2 Expansion Connector Pin Assignments (continued)

Pin Number

Signal Mnemonic

Signal Name And Description

35 — 37 FC2/

CS5

FC1/

CS4

FC0/

CS3

FUNCTION CODES – Three-state output signals that

identify the processor state and address space of the

current bus cycle.

CHIP SELECTS 3—5 – Output signals that select

peripheral/memory devices at programmed addresses.

BGACK

CS2

BUS GRANT ACKNOWLEDGE – Active-low input

signal that indicates that an external device has

assumed control of the bus.

CHIP SELECT 2 – Output signal that selects

peripheral/ memory devices at programmed addresses.

CS1

BUS GRANT – Active-low output signal that indicates

that the current bus cycle is complete and the

MC68332 has relinquished the bus.

CHIP SELECT 1 – Output signal that selects

peripheral/ memory devices at programmed addresses.

CS0

BUS REQUEST – Active-low input signal that indicates

that an external device requires bus master-ship.

CHIP SELECT 0 – Output signal that selects

peripheral/ memory devices at programmed addresses.

41 — 47

IRQ1

—

IRQ7

INTERRUPT REQUEST (1—7) – Seven active-low

input lines used to request MCU synchronous

interrupts. IRQ7 has the highest priority.

BERR

BUS ERROR – Active-low input signal that indicates

that an erroneous bus operation is being attempted.

1 2 ... 56 57 58 59 60 61 62 63 64 65 66 67 68

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Motorola M68CPU32BUG User Manual Page 61

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