Motorola CPCI-6115 Service Manual Page 21

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Chapter 1
CPCI-6200 Installation and Use (6806800J66C)
21
Introduction
1.1 Features
The CPCI-6200 is a high performance, hot swappable universal Compact PCI board based on
the MPC8572 integrated processor.
Table 1-1 Summary of Features
Function Features
Processor
Host Controller
Memory Controller
One 8572 integrated processor
Two e500 cores with integrated 1 MB L2 cache
32 KB data and instruction cache on each core
Core frequency from 1.3 to 1.5 GHz
Two integrated DDR3 SDRAM controllers
Two integrated four-channel DMA controller
Two integrated PCI Express interfaces (8 lanes of 2.5 Gb/s
each)
Four integrated 10/100/1000 Ethernet controllers
One integrated DUART
Two integrated I
2
C controllers
One integrated programmable interrupt controller
One integrated local bus controller
System Memory Two banks of DDR3 SDRAM with error-correcting code
(ECC)
Supports 2 or 4 GB
Provides up to 800 MHz DDR3 data rate
I
2
C One 8 KB VPD serial EEPROM
Two 64 KB user configuration serial EEPROMs
One real time clock (RTC) with battery back-up
Dual temperature sensors
Two SPDs for memory
Connection to the PCIE expander and RTM
Flash 128 MB soldered flash with two alternate 1 MB boot
sectors that can be selected via a hardware switch
HW switch or SW bit write protection for the entire
logical bank
Minimum of 4 GB user flash
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