Motorola CPCI-6115 Service Manual Page 148

  • Download
  • Add to my manuals
  • Print
  • Page
    / 196
  • Table of contents
  • BOOKMARKS
  • Rated. / 5. Based on customer reviews
Page view 147
Memory Maps and Addresses
CPCI-6200 Installation and Use (6806800J66C)
148
7.4.5 Interrupt Register 1
This register may be read by the system software to determine which of the Ethernet PHYs
originated their combined (OR'd) interrupt.
Table 7-13 Interrupt Register 1, 0xF200_0004
Bit Field Operation Reset
7RSVDR 0
6RSVDR 0
5RSVDR 0
4RSVDR 0
3PHY 4R 0
2PHY 3R 0
1PHY 2R 0
0PHY 1R 0
Table 7-14 Interrupt Register 1 Field Definition
RSVD Reserved
PHY 4 TSEC4 Interrupt
1 TSEC4 interrupt is asserted.
0 TSEC4 interrupt is not asserted.
PHY 3 TSEC3 Interrupt
1 TSEC3 interrupt is asserted.
TSEC3 interrupt is not asserted.
PHY 2 TSEC2 Interrupt
1 TSEC2 interrupt is asserted.
0 TSEC2 interrupt is not asserted.
PHY 1 TSEC1 Interrupt
1 TSEC1 interrupt is asserted.
0 TSEC1 interrupt is not asserted.
Page view 147
1 2 ... 143 144 145 146 147 148 149 150 151 152 153 ... 195 196

Comments to this Manuals

No comments