Motorola M68000 User Manual Page 75
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Floating Point Instructions
5-64 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
FLOGN Log
e
FLOGN
(MC6888X, M68040FPSP)
Operation: Log
e
of Source → FPn
Assembler FLOGN. < fmt > < ea > ,FPn
Syntax: FLOGN.X FPm,FPn
FLOGN.X FPn
Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and
calculates the natural logarithm of that number. Stores the result in the destination
floating-point data register. This function is not defined for input values less than zero.
Operation Table:
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the OPERR bit in the floating-point status register exception byte.
3. Sets the DZ bit in the floating-point status register exception byte.
Floating-Point Status Register:
Condition Codes: Affected as described in 3.6.2 Conditional Testing.
Quotient Byte: Not affected.
Exception Byte: BSUN Cleared
SNAN Refer to 1.6.5 Not-A-Numbers.
OPERR Set if the source operand is < 0; cleared
otherwise.
OVFL Cleared
UNFL Cleared
DZ Set if the source is ± 0; cleared otherwise
INEX2 Refer to inexact result in the appropriate
user’s manual.
INEX1 If < fmt > is packed, refer to inexact result on
decimal input in the appropriate user’s
manual; cleared otherwise.
Accrued Exception Byte: Affected as described in IEEE exception and trap compati-
bility in the appropriate user’s manual.
DESTINATION
SOURCE
1
+ In Range – + Zero – + Infinity –
Result
In(x) NAN
2
– inf
3
+ inf NAN
2
- MOTOROLA 1
- M68000 FAMILY 1
- TABLE OF CONTENTS 2
- LIST OF FIGURES 8
- LIST OF FIGURES (Concluded) 9
- LIST OF TABLES 10
- LIST OF TABLES (Continued) 11
- SECTION 5 12
- FLOATING POINT INSTRUCTIONS 12
- Floating-Point Absolute Value 15
- Arc Cosine 19
- Floating-Point Add 22
- FADD Floating-Point Add FADD 23
- FASIN Arc Sine FASIN 25
- FATAN Arc Tangent FATAN 28
- Floating-Point Compare FCMP 36
- FCOS Cosine FCOS 39
- FCOSH Hyperbolic Cosine FCOSH 42
- Hyperbolic Cosine FCOSH 43
- Hyperbolic Cosine FCOSH 44
- Decrement, and Branch 45
- Floating-Point Divide FDIV 47
- FETOXM1 e 54
- FGETEXP Get Exponent FGETEXP 57
- FGETMAN Get Mantissa FGETMAN 60
- FINT Integer Part FINT 63
- FLOG10 Log 69
- FLOG2 Log 72
- FLOGN Log 75
- FLOGNP1 Log 78
- FMOD Modulo Remainder FMOD 81
- ⋅), but all 84
- < EA > TO REGISTER 86
- REGISTER—TO-MEMORY 89
- Move Floating-Point FMOVE 91
- System Control Register 91
- Move Constant ROM FMOVECR 94
- Data Registers 100
- Control Registers 102
- Floating-Point Multiply FMUL 105
- Floating-Point Negate FNEG 109
- FNOP No Operation FNOP 113
- FREM IEEE Remainder FREM 115
- FSCALE Scale Exponent FSCALE 118
- Floating Point Instructions 121
- FSIN Sine FSIN 129
- FSINH Hyperbolic Sine FSINH 136
- Floating-Point Subtract FSUB 143
- FTAN Tangent FTAN 147
- Hyperbolic Tangent FTANH 150
- FTENTOX 10 153
- FTENTOX 153
- DESTINATION 158
- FTWOTOX 2 161
- FTWOTOX 161
- SECTION 6 164
- ANDI ANDI 165
- Invalidate Cache Lines 166
- Coprocessor 168
- Restore Functions 168
- Coprocessor Save Function 170
- 1514131211109876543210 171
- EORI EORI 173
- Restore Internal FRESTORE 174
- Floating-Point State 174
- MOVE MOVE 180
- Move Control Register MOVEC 185
- Move Address Space MOVES 187
- ORI ORI 190
- 1111000001001COUNT REGISTER 194
- 0000000000 MC68851 CONDITION 194
- 16-BIT DISPLACEMENT 194
- 1111000000 196
- EFFECTIVE ADDRESS 196
- MODE REGISTER 196
- 0 0 1 MODE 0 0 MASK FC 196
- Flush ATC Entries PFLUSH 198
- PFLUSH PFLUSH 201
- PFLUSHA PFLUSHA 201
- 1010000000000000 204
- 001000R/ W0000 FC 207
- SRP, CRP, and TC Registers 211
- MMU Status Register 212
- TT Registers 213
- 011000R/W000000000 214
- ACx Registers 215
- Move PMMU Register PMOVE 216
- 1111000101 221
- PMMU Save Function PSAVE 222
- Set on PMMU Condition PScc 225
- Test a Logical Address PTEST 226
- (MC68030 only) 228
- 1111000001111 OPMODE 242
- Validate a Pointer PVALID 243
- Reset External Devices RESET 246
- Return from Exception RTE 247
- 0100111001110010 248
- IMMEDIATE DATA 248
- SECTION 7 250
- CPU32 INSTRUCTIONS 250
- Enter Background Mode 253
- (CPU32) 253
- Low-Power Stop 254
- TBLS TBLS 255
- TBLU TBLU 260
- CPU32 Instructions 265
- SECTION 8 266
- INSTRUCTION FORMAT SUMMARY 266
- Instruction Format Summary 286
- X AND BACX REGISTERS 290
- TBLU, TBLUN 293
- TBLS, TBLSN 293
- DATA REGISTER INTERPOLATE 294
- FLOGNP1 295
- FETOXM1 295
- FRESTORE 303
- FTRAPcc 303
- APPENDIX A 306
- PROCESSOR INSTRUCTION SUMMARY 306
- Processor Instruction Summary 317
- Mnemonic Description 317
- (Continued) 318
- Data Addressing Modes 321
- A.2 MC68020 PROCESSORS 322
- (Concluded) 324
- Addressing Modes Syntax 325
- A.3 MC68030 PROCESSORS 326
- A.4 MC68040 PROCESSORS 330
- A.6 MC68851 COPROCESSORS 336
- APPENDIX B 338
- Assignment 339
- B.2 EXCEPTION STACK FRAMES 340
- Frame, Format $4 342
- Format $9 343
- 15 031 24 23 16 349
- VERSION $41 349
- (RESERVED) 349
- APPENDIX C 352
- S-RECORD OUTPUT FORMAT 352
- C.2 S-RECORD TYPES 353
- C.3 S-RECORD CREATION 354
- Table C-2. ASCII Code 356
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