Motorola M68000 User Manual download pdf (Page 45)

Floating Point Instructions

5-34 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

FDBcc Floating-Point Test Condition, FDBcc

Decrement, and Branch

(MC6888X, MC68040)

Operation: If Condition True

Then No Operation

Else Dn – 1 → Dn

If Dn ≠ – 1

Then PC + d

→ PC

Else Execute Next Instruction

Assembler

Syntax: FDBcc Dn, < label >

Attributes: Unsized

Description: This instruction is a looping primitive of three parameters: a ﬂoating-point

condition, a counter (data register), and a 16-bit displacement. The instruction ﬁrst tests

the condition to determine if the termination condition for the loop has been met, and if

so, execution continues with the next instruction in the instruction stream. If the

termination condition is not true, the low-order 16 bits of the counter register are

decremented by one. If the result is – 1, the count is exhausted, and execution

continues with the next instruction. If the result is not equal to – 1, execution continues

at the location speciﬁed by the current value of the program counter plus the sign-

extended 16-bit displacement. The value of the program counter used in the branch

address calculation is the address of the displacement word.

The conditional specifier cc selects any one of the 32 floating- point conditional tests

as described in 3.6.2 Conditional Testing.

Floating-Point Status Register:

Condition Codes: Not affected.

Quotient Byte: Not affected.

Exception Byte: BSUN Set if the NAN condition code is set and the

condition selected is an IEEE nonaware test.

SNAN Not Affected.

OPERR Not Affected.

OVFL Not Affected.

UNFL Not Affected.

DZ Not Affected.

NEX2 Not Affected.

INEX1 Not Affected.

Accrued Exception Byte: The IOP bit is set if the BSUN bit is set in the exception

byte. No other bit is affected.

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Motorola M68000 User Manual Page 45