Motorola M68000 User Manual download pdf (Page 254)

CPU32 Instructions

MOTOROLA

M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL

7-5

LPSTOP

Low-Power Stop

LPSTOP

(CPU32)

Operation:

If Supervisor State

Immediate Data

→

Interrupt Mask

→

External Bus Interface (EBI)

STOP

Else TRAP

Assembler

Syntax:

LPSTOP # < data >

Attributes:

Size = (Word) Privileged

Description:

The immediate operand moves into the entire status register, the program

counter advances to point to the next instruction, and the processor stops fetching and

executing instructions. A CPU LPSTOP broadcast cycle is executed to CPU space $3

to copy the updated interrupt mask to the external bus interface (EBI). The internal

clocks are stopped.

Instruction execution resumes when a trace, interrupt, or reset exception occurs. A

trace exception will occur if the trace state is on when the LPSTOP instruction is

executed. If an interrupt request is asserted with a higher priority that the current

priority level set by the new status register value, an interrupt exception occurs;

otherwise, the interrupt request is ignored. If the bit of the immediate data

corresponding to the S-bit is off, execution of the instruction will cause a privilege

violation. An external reset always initiates reset exception processing.

Condition Codes:

Set according to the immediate operand.

Instruction Format:

Instruction Fields:

Immediate ﬁeld—Speciﬁes the data to be loaded into the status register.

1514131211109876543210

1111100000000000

0000000111000000

IMMEDIATE DATA

1 2 ... 249 250 251 252 253 254 255 256 257 258 259 ... 356 357

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Motorola M68000 User Manual Page 254

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