Motorola CPU32 User's Guide download pdf (Page 81)

CPU32

SIGNAL

NAME

E2480A

TIMING

CONNECTOR

ANALYZER

BIT

TIMING

LABEL

TIMING SUBLABEL

Timing Connector J4, Timing Pod 4

ADDR16 37 0 ADDR PORT A

ADDR17 35 1 ADDR PORT A

ADDR18 33 2 ADDR PORT A

FC0/CS3 31 3 PORT C CSx

FC1/CS4 29 4 PORT C CSx

FC2/CS5 27 5 PORT C CSx

ADDR19/~CS6 25 6 ADDR PORT C CSx

ADDR20/~CS7 23 7 ADDR PORT C CSx

ADDR21/~CS8 21 8 ADDR PORT C CSx

ADDR22/~CS9 19 9 ADDR PORT C CSx

ADDR23/~CS10 17 10 ADDR PORT C CSx

na 15 11

na 13 12

na 11 13

~IFetch/DS1 9 14

~IPipe/DS0 7 15

~Bkpt/DSclk 5 CLK

NOTE: Signals A19—A23 and CS6—CS10 are multiplexed onto the same pins, and the default

configuration of the logic analyzer assumes that signals A19—A23 are valid. If any of the chip

selects, CS6—CS10, are being used then the bits associated with A19—A23 should be

removed from the ADDR label via the format menu in the logic analyzer. This corresponds to

bits 3—7 of pod A4. This results in the display of correct address information in the ADDR

field of the listing menu and presents only valid address bus bits to the ADDR field in the

trigger menu.

Reference

Signal-to-connector mapping (Timing)

4–10 E2480A Motorola CPU32 Preprocessor Interface

1 2 ... 76 77 78 79 80 81 82 83 84 85 86 ... 106 107

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Motorola CPU32 User's Guide Page 81