Motorola MVME712AM Installation Guide download pdf (Page 19)

Requirements

MVME197IG/D1 1-3

The ECDM (Error Correction and Data Multiplexer) ASIC multiplexes

between four data paths on the DRAM array. Since the device handles 16 bits,

four such devices are required on the MVME197 to accommodate the 64-bit

data bus of the MC88110 RISC microprocessor. Single-bit error correction and

double-bit detection is performed in the ECDM.

The PCCchip2 (Peripheral Channel Controller) ASIC provides two tick timers

and the interface to the LAN chip, the SCSI chip, the serial port chip, the

printer port, and the BBRAM (Battery Backup RAM).

The VMEchip2 ASIC provides a VMEbus interface. The VMEchip2 includes

two tick timers, a watchdog timer, programmable map decoders for the master

and slave interfaces, and a VMEbus to/from the local peripheral bus DMA

controller, a VMEbus to/from the local peripheral bus non-DMA

programmed access interface, a VMEbus interrupter, a VMEbus system

controller, a VMEbus interrupt handler, and a VMEbus requester.

The local peripheral bus to VMEbus transfers can be D8, D16, or D32.

VMEchip2 DMA transfers to the VMEbus, however, can be 64 bits wide as

Block Transfer (BLT).

Requirements

All MVME197 boards are designed to conform to the requirements of the

following documents:

❏ VMEbus Specification (IEEE 1014-87)

❏ EIA-232-D Serial Interface Specification, EIA

❏ SCSI Specification, ANSI

Features

These are some of the major features of the MVME197DP/SP single board

computers:

❏ Single MC88110 RISC Microprocessor with an MC88410 Cache Controller

(MVME197SP module series)

❏ Dual MC88110 RISC Microprocessors, each with one MC88410 Cache

Controller (MVME197DP module series)

❏ 256 kilobytes of external cache per processor, controlled by the MC88410

(MVME197DP and MVME197SP module series)

❏ 128 or 256 megabytes of 64-bit Dynamic Random Access Memory (DRAM)

with Error Checking and Correction (ECC)

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Motorola MVME712AM Installation Guide Page 19