DSP56303
Target Applications
MOTOROLA DSP56303P/D 3
• Off-chip memory expansion
– Data memory expansion to two 256 K x 24-bit word memory spaces
– Program memory expansion to one 256 K x 24-bit word memory space
– External memory expansion port
– Chip select logic requires no additional circuitry to interface to SRAMs and
SSRAMs
– On-chip DRAM controller requires no additional circuitry to interface to DRAMs
• On-chip peripherals
– 8-bit parallel Host Interface (HI08), ISA-compatible bus interface, providing a
cost-effective solution for applications not requiring the PCI bus
– Two Enhanced Synchronous Serial Interfaces (ESSI)
– Serial Communications Interface (SCI) with baud rate generator
– Triple timer module
– Up to thirty-four programmable General Purpose I/O pins (GPIO), depending on
which peripherals are enabled
• Reduced power dissipation
– Very low power CMOS design
– Wait and Stop low power standby modes
– Fully-static logic, operation frequency down to DC
– Optimized power management circuitry
TARGET APPLICATIONS
The DSP56303 is intended for use in telecommunication applications, such as multi-line
voice/data/fax processing, videoconferencing, audio applications, control, and general
digital signal processing.
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