Motorola ColdFire MCF5282 User Manual download pdf (Page 5)

Possible Cache Corruption after Setting CACR[CINV]

MCF5282 Device Errata, Rev. 1.5

Freescale Semiconductor 5

6 Possible Cache Corruption after Setting

CACR[CINV]

6.1 Description

The cache on the MCF5282 was enhanced to function as a unified data and instruction cache, an

instruction cache, or an operand cache. The cache function and organization is controlled by the cache

control register (CACR). The CINV (Bit 24 = cache invalidate) bit in the CACR causes a cache clear. If

the cache is configured as a unified cache and the CINV bit is set, the scope of the cache clear is controlled

by two other bits in the CACR, INVI (BIT 21 = CINV instruction cache only) and INVD (BIT 20 = CINV

data cache only). These bits allow the entire cache, just the instruction portion of the cache, or just the data

portion of the cache to be cleared. If a write to the CACR is performed to clear the cache (CINV = BIT 24

set) and only a partial clear will be done (INVI = BIT 21 or INVD = BIT20 set), then cache corruption may

occur.

6.2 Workaround

All loads of the CACR that perform a cache clear operation (CINV = BIT 24) should be followed

immediately by a NOP instruction. This avoids the cache corruption problem.

DATECODES AFFECTED: All

7 Incorrect Operation of CACR[CFRZ]

7.1 Description

The cache on the ColdFire V2 is controlled by the cache control register (CACR). When CACR[CFRZ] is

set, the cache freeze function is enabled and no valid cache array entry will be displaced. However, this

feature does not work as specified, sometimes allowing valid lines to be displaced when CACR[CFRZ] is

enabled.

This will not cause any corrupted accesses. However, there could be cache misses for data that was

originally loaded into the cache but was subsequently deallocated even though the CACR[CFRZ] bit was

set.

Also, incoherent cache states are possible when a frozen cache is cleared via the CINV (bit 24 = cache

invalidate) bit in the CACR.

7.2 Workaround

• Unfreeze the cache by clearing CACR[CFRZ] when invalidating the cache using the

CACR[CINV] bit.

• Use the internal SRAM to store critical code/data if the system cannot handle a potential cache

miss.

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