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15-6 MC68VZ328 User’s Manual
Programming Model
15.4.2 PWM 1 Sample Register
This register serves as the input to the FIFO. When successive audio sample values are written to this
register, they are automatically loaded into the FIFO in big-endian format. If 16-bit words are loaded, high
byte is first placed into the 8-bit FIFO, and then low byte. When individual sample bytes are being written,
they must be written to the low byte (SAMPLE1) only. The pulse-width modulator will revert to free
running at the duty-cycle setting that was set last until the FIFO is reloaded or the pulse-width modulator is
disabled. If the value in this register is higher than the PERIOD + 1, the output will never be reset, which
results in a 100-percent duty cycle. The register bit assignments are shown in the following register
display. The register settings are described in Table 15-2.
PWMS1 PWM 1 Sample Register 0x(FF)FFF502
BIT
15
14 13 12 11 10 987654321
BIT
0
SAMPLE0 SAMPLE1
TYPE rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
RESET
XXXXXXXXXXXXXXXX
0xXXXX
Table 15-2. PWM 1 Sample Register Description
Name Description Setting
SAMPLE0
Bits 15–8
Sample 0—This field represents the high byte of a two-sample word. This byte is pre-
sented to the pulse-width modulator before the SAMPLE1 field.
None
SAMPLE1
Bits 7–0
Sample 1—This field represents the low byte of a two-sample word. This byte will be
presented to the pulse-width modulator after the SAMPLE0 field. When used with single
8-bit samples, data must be written to this byte.
None
- User’s Manual 1
- Contents 3
- Table of Contents v 5
- Table of Contents vii 7
- Table of Contents ix 9
- Chapter 14 10
- Chapter 15 10
- Pulse-Width Modulator 1 and 2 10
- Table of Contents xi 11
- Chapter 18 12
- Application Guide 12
- Chapter 19 12
- Electrical Characteristics 12
- Table of Contents xiii 13
- List of Figures 15
- List of Figures xvii 17
- List of Tables 19
- List of Tables xxi 21
- List of Tables xxiii 23
- List of Examples 25
- About This Book 27
- Audience 27
- Organization 27
- Suggested Reading 29
- Conventions 29
- Chapter 1 31
- Introduction 31
- 1-2 MC68VZ328 User’s Manual 32
- Features of the MC68VZ328 32
- Introduction 1-3 33
- 1.2 CPU 34
- 1.2.1 CPU Programming Model 35
- 1-6 MC68VZ328 User’s Manual 36
- Table 1-1. Address Modes 36
- Introduction 1-7 37
- 1.3.1 Memory Controller 38
- 1.3.3 System Control 39
- 1.3.4 Chip-Select Logic 39
- 1.3.5 DRAM Controller 39
- 1.3.6 LCD Controller 39
- 1.3.7 Interrupt Controller 39
- Modules of the MC68VZ328 40
- 1.3.15 Bootstrap Mode 41
- Chapter 2 43
- Signal Descriptions 43
- 2-2 MC68VZ328 User’s Manual 44
- Signals Grouped by Function 44
- Signal Descriptions 2-3 45
- 2-4 MC68VZ328 User’s Manual 46
- 2.4 Address Bus Signals 47
- 2.5 Data Bus Signals 47
- 2.6 Bus Control Signals 48
- 2.8 LCD Controller Signals 49
- 2.10 Timer Signals 50
- Signal Descriptions 2-9 51
- SDRAM Interface Signals 52
- Signal Descriptions 2-11 53
- Chapter 3 55
- Memory Map 55
- 3.1 Programmer’s Memory Map 56
- Memory Map 3-3 57
- 3-4 MC68VZ328 User’s Manual 58
- Programmer’s Memory Map 58
- Memory Map 3-5 59
- 3-6 MC68VZ328 User’s Manual 60
- Memory Map 3-7 61
- 3-8 MC68VZ328 User’s Manual 62
- Memory Map 3-9 63
- Memory Map 3-11 65
- Memory Map 3-13 67
- Chapter 4 69
- Control Module 69
- 4-2 MC68VZ328 User’s Manual 70
- CGM Operational Overview 71
- 4.3.1 CLK32 Clock Signal 72
- 4.3.2 PLLCLK Clock Signal 72
- Eqn. 4-2 74
- 4.4 CGM Programming Model 76
- CGM Programming Model 77
- 4.5.1 Operating the PCM 79
- 4.5.3 Burst Mode Operation 80
- 4.5.4 Power Control Register 82
- Chapter 5 83
- System Control 83
- 5.2 Programming Model 84
- System Control 5-3 85
- 5-4 MC68VZ328 User’s Manual 86
- 5.2.3 ID Register 87
- 5-6 MC68VZ328 User’s Manual 88
- Chapter 6 89
- Chip-Select Logic 89
- 6.2 Chip-Select Operation 90
- Chip-Select Logic 6-3 91
- 6.3 Programming Model 92
- Chip-Select Logic 6-5 93
- Chip-Select Logic 6-7 95
- 6.3.3 Chip-Select Registers 96
- Chip-Select Logic 6-9 97
- Chip-Select Logic 6-11 99
- Programming Model 100
- Chip-Select Logic 6-13 101
- Chip-Select Logic 6-15 103
- Chip-Select Logic 6-17 105
- Chip-Select Size 106
- Unprotected Size 106
- Chip-Select Logic 6-19 107
- Chip-Select Logic 6-21 109
- Chapter 7 111
- DRAM Controller 111
- 7-2 MC68VZ328 User’s Manual 112
- 7.2.1 Address Multiplexing 113
- 7-4 MC68VZ328 User’s Manual 114
- DRAM Controller Operation 114
- DRAM Controller 7-5 115
- 7-6 MC68VZ328 User’s Manual 116
- 7.2.2 DTACK Generation 117
- 7.2.3 Refresh Control 117
- 7.2.4 LCD Interface 118
- 7.2.5 8-Bit Mode 119
- 7.2.6 Low-Power Standby Mode 119
- DRAM Controller 7-11 121
- 7.3 Programming Model 122
- DRAM Controller 7-13 123
- 7.3.2 DRAM Control Register 124
- DRAM Controller 7-15 125
- 7.3.3 SDRAM Control Register 126
- DRAM Controller 7-17 127
- Chapter 8 129
- LCD Controller 129
- 8-2 MC68VZ328 User’s Manual 130
- LCD Controller Operation 130
- LCD Controller 8-3 131
- 8-4 MC68VZ328 User’s Manual 132
- LCD Controller 8-5 133
- 8-6 MC68VZ328 User’s Manual 134
- LCD Controller 8-7 135
- 8.2.3 Using Low-Power Mode 136
- 8.2.5 Self-Refresh Mode 137
- 8.3 Programming Model 138
- LCD Controller 8-11 139
- LCD Controller 8-13 141
- LCD Controller 8-15 143
- LCD Controller 8-17 145
- LCD Controller 8-19 147
- LCD Controller 8-21 149
- 8.4 Programming Example 150
- Chapter 9 151
- Interrupt Controller 151
- 9.1 Interrupt Processing 152
- 9.2 Exception Vectors 153
- 9.3 Reset 154
- Interrupt Controller 9-5 155
- 9.5 Vector Generation 156
- 9.6 Programming Model 157
- 9-8 MC68VZ328 User’s Manual 158
- Interrupt Controller 9-9 159
- Interrupt Controller 9-11 161
- Interrupt Controller 9-13 163
- Interrupt Controller 9-15 165
- Interrupt Controller 9-17 167
- Interrupt Controller 9-19 169
- 9.7 Keyboard Interrupts 170
- 9.8 Pen Interrupts 170
- Chapter 10 171
- I/O Ports 171
- 10.2.1 Warm Reset 172
- 10.2.2 Power-up Reset 173
- 10.3 I/O Port Operation 174
- I/O Ports 10-5 175
- 10.4 Programming Model 176
- I/O Ports 10-7 177
- 10.4.2 Port B Registers 178
- I/O Ports 10-9 179
- 10.4.3 Port C Registers 181
- I/O Ports 10-13 183
- Table 10-16 184
- 10.4.4 Port D Operation 185
- 10.4.5 Port D Registers 186
- I/O Ports 10-17 187
- I/O Ports 10-19 189
- 10.4.6 Port E Registers 191
- I/O Ports 10-23 193
- 10.4.7 Port F Registers 194
- I/O Ports 10-25 195
- I/O Ports 10-27 197
- 10.4.8 Port G Registers 198
- I/O Ports 10-29 199
- 10.4.9 Port J Registers 201
- I/O Ports 10-33 203
- 10.4.10 Port K Registers 204
- I/O Ports 10-35 205
- 10.4.11 Port M Registers 207
- I/O Ports 10-39 209
- Table 10-55 210
- Chapter 11 211
- Real-Time Clock 211
- 11.1 RTC Overview 212
- 11.1.2 Time-of-Day Counter 213
- 11.1.3 Alarm 213
- 11.1.4 Watchdog Timer 214
- 11.1.6 Minute Stopwatch 214
- 11.2 Programming Model 215
- 11.2.3 RTC Alarm Register 217
- Real-Time Clock 11-9 219
- 11.2.6 RTC Control Register 220
- Real-Time Clock 11-11 221
- Real-Time Clock 11-13 223
- Chapter 12 225
- General-Purpose Timers 225
- 12.1.2.1 Restart Mode 226
- 12.1.2.2 Free-Running Mode 226
- 12.1.4 TOUT/TIN/PB6 Pin 227
- 12.1.5 Cascaded Timers 228
- General-Purpose Timers 12-5 229
- 12.2 Programming Model 230
- General-Purpose Timers 12-7 231
- General-Purpose Timers 12-9 233
- General-Purpose Timers 12-11 235
- Chapter 13 237
- 13.2 SPI 1 Operation 238
- 13.2.4 SPI 1 Signals 239
- SPI 1 Programming Model 240
- Table 13-3 242
- 13.3.5 SPI 1 Test Register 246
- 13.4 SPI 2 Overview 247
- 13.5 SPI 2 Operation 248
- 13.5.2 SPI 2 Signals 249
- 13.6.1 SPI 2 Data Register 250
- SPI 2 Programming Model 251
- Universal Asynchronous 253
- Receiver/Transmitter 1 and 2 253
- 14.2 Serial Operation 254
- 14.2.2 IrDA Mode 255
- 14.3 UART Operation 256
- UART Operation 257
- 14.3.2 Receiver Operation 258
- 14.3.3.1 Divider 259
- 14.3.3.3 Integer Prescaler 261
- 14.4 Programming Model 262
- 15.2 PWM 1 284
- 15.3 PWM Operation 285
- 15.4 Programming Model 286
- 15.4.2 PWM 1 Sample Register 288
- 15.4.3 PWM 1 Period Register 289
- 15.5 PWM 2 290
- 15.5.2 PWM 2 Period Register 291
- Chapter 16 293
- In-Circuit Emulation 293
- 16.1 ICE Operation 294
- In-Circuit Emulation 16-3 295
- 16.2 Programming Model 296
- In-Circuit Emulation 16-5 297
- Mask Register 298
- In-Circuit Emulation 16-7 299
- In-Circuit Emulation 16-9 301
- 16.3.1 Host Interface 303
- 16.3.5 Optional Trace Module 304
- In-Circuit Emulation 16-13 305
- Chapter 17 307
- Bootstrap Mode 307
- Bootstrap Mode Operation 308
- Bootstrap Mode 17-3 309
- Bootstrap Mode 17-5 311
- 17.2 Bootloader Flowchart 312
- Bootstrap Mode 17-7 313
- 17.3 Special Notes 314
- AC Electrical Characteristics 318
- “Chip-Select Logic.” 326
- Wait State) 329
- (LCD Bus Master) 330
- Timing Parameters 331
- Timing Parameters (Continued) 333
- Latency = 1) 335
- Controller.” 336
- Register = 1) 341
- “DRAM Controller.” 342
- Interface 1 and 2.” 350
- 19.3.32 Normal Mode Timing 351
- Chapter 20 353
- Mechanical Data and Ordering 353
- Information 353
- 20.2 TQFP Pin Assignments 354
- TQFP Package Dimensions 355
- DATA_READY 356
- MAPBGA Package Dimensions 357
- CASE 1242A-03 357
- 20.6 PCB Finish Requirement 358
- Index Index-i 359
- Index Index-iii 361
- Index Index-v 363
- Index Index-vii 365
- Index Index-ix 367
- Index Index-xi 369
- Index Index-xiii 371
- Index Index-xv 373
- Index Index-xvii 375
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