Motorola DSP56012 User Manual Page 17
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- Table of contents
- BOOKMARKS
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Motorola xvii
List of Tables
Table 1-1 High True / Low True Signal Conventions. . . . . . . . . . . . . . . . . . 1-6
Table 1-2 DSP56012 Internal Memory Configurations . . . . . . . . . . . . . . . . 1-7
Table 1-3 Interrupt Starting Addresses and Sources . . . . . . . . . . . . . . . 1-13
Table 1-4 Internal Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . 1-15
Table 1-5 On-chip Peripheral Memory Map . . . . . . . . . . . . . . . . . . . . . . . 1-17
Table 2-1 DSP56012 Functional Signal Groupings . . . . . . . . . . . . . . . . . . 2-3
Table 2-2 Power Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Table 2-3 Grounds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Table 2-4 Phase Lock Loop Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Table 2-5 Interrupt and Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Table 2-6 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Table 2-7 Serial Host Interface (SHI) Signals . . . . . . . . . . . . . . . . . . . . . 2-13
Table 2-8 Serial Audio Interface (SAI) Receive Signals . . . . . . . . . . . . . . 2-16
Table 2-9 Serial Audio Interface (SAI) Transmit Signals. . . . . . . . . . . . . . 2-17
Table 2-10 General Purpose I/O (GPIO) Signals . . . . . . . . . . . . . . . . . . . . 2-18
Table 2-11 Digital Audio Interface (DAX) Signals . . . . . . . . . . . . . . . . . . . . 2-18
Table 2-12 On-Chip Emulation Port (OnCE) Signals . . . . . . . . . . . . . . . . 2-19
Table 3-1 Internal Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Table 3-2 Internal I/O Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Table 3-3 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
Table 3-4 Interrupt Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
- DSP56012 1
- Table of Contents 3
- Motorola v 5
- Motorola vii 7
- Motorola ix 9
- Motorola xi 11
- List of Figures 13
- List of Tables 17
- Motorola xix 19
- SECTION 1 21
- OVERVIEW 21
- Overview 22
- 1.1 INTRODUCTION 23
- 1.1.1 Manual Organization 24
- 1.1.2 Manual Conventions 25
- 1.2 DSP56012 FEATURES 26
- DSP56012 Features 27
- 1.3.1 Peripheral Modules 30
- 1.3.2 DSP Core Processor 30
- 1.3.3 Memories 33
- 1.3.4 Input/Output 36
- SECTION 2 41
- SIGNAL DESCRIPTIONS 41
- Signal Descriptions 42
- 2.1 SIGNAL GROUPINGS 43
- Figure 2-1 DSP56012 Signals 44
- 2.2 POWER 45
- 2.3 GROUND 46
- 2.4 PHASE LOCK LOOP (PLL) 47
- Interrupt and Mode Control 48
- 2.6 HOST INTERFACE (HI) 50
- Serial Host Interface (SHI) 54
- 2.8.1 SAI Receive Section 56
- 2.8.2 SAI Transmit Section 57
- 2.11 OnCE PORT 59
- OnCE Port 60
- SECTION 3 61
- MEMORY, OPERATING MODES 61
- AND INTERRUPTS 61
- 3.1 INTRODUCTION 63
- 3.2.1 X and Y Data ROM 64
- 3.2.2 Bootstrap ROM 64
- 3.3.1 Reserved Memory Spaces 65
- 3.3.3 Internal I/O Memory Map 70
- 3.4.3 Stop Delay (SD)—Bit 6 72
- 3.5 OPERATING MODES 73
- Operating Modes 74
- Interrupt Priority Register 75
- AA0292.11 76
- Operation on Hardware Reset 80
- SECTION 4 81
- PARALLEL HOST INTERFACE 81
- 4.1 INTRODUCTION 83
- 4.2 PORT B CONFIGURATION 83
- Port B Configuration 84
- 4.3 PROGRAMMING THE GPIO 88
- 4.4 HOST INTERFACE (HI) 89
- 4.4.1 HI Features 90
- 4.4.2 HI Block Diagram 91
- 4.4.3 HI—DSP Viewpoint 92
- Parallel Host Interface 101
- Host Interface (HI) 101
- Command Vector Register (CVR) 109
- 4.4.6 HI Signals 115
- 4.4.7 Servicing the HI 117
- DSP56012 Technical Data 118
- AA0323.11 120
- Figure 4-27 Host Command 132
- * ;Now wait for interrupt 133
- SECTION 5 149
- SERIAL HOST INTERFACE 149
- Serial Host Interface 150
- 5.1 INTRODUCTION 151
- 5.3 SHI CLOCK GENERATOR 153
- 5.6 CHARACTERISTICS OF THE I 168
- 5.6.1 Overview 168
- Characteristics Of The I 169
- C Data Transfer Formats 170
- 5.7.1 SPI Slave Mode 171
- 5.7.2 SPI Master Mode 172
- C Slave Mode 173
- C Master Mode 175
- SECTION 6 179
- SERIAL AUDIO INTERFACE 179
- Serial Audio Interface 180
- 6.1 INTRODUCTION 181
- 6.2.1 Baud-Rate Generator 182
- Transmitter Sections 202
- 6.4.4 SAI State Machine 203
- Programming Considerations 204
- SECTION 7 205
- 7.1 INTRODUCTION 207
- 7.2 GPIO PROGRAMMING MODEL 207
- 7.3 GPIO REGISTER (GPIOR) 207
- GPIO Register (GPIOR) 209
- SECTION 8 211
- DIGITAL AUDIO TRANSMITTER 211
- Digital Audio Transmitter 212
- 8.1 OVERVIEW 213
- 8.2 DAX SIGNALS 214
- 8.3 DAX FUNCTIONAL OVERVIEW 215
- 8.4 DAX PROGRAMMING MODEL 216
- 8.5 DAX INTERNAL ARCHITECTURE 216
- DAX Internal Architecture 217
- 8.5.8 DAX Biphase Encoder 222
- 8.5.9 DAX Preamble Generator 222
- 8.5.10 DAX Clock Multiplexer 223
- 8.5.11 DAX State Machine 224
- APPENDIX A 227
- BOOTSTRAP ROM CONTENTS 227
- Bootstrap ROM Contents 228
- A.1 INTRODUCTION 229
- A.2 BOOTSTRAPPING THE DSP 229
- A.3 BOOTSTRAP PROGRAM LISTING 230
- APPENDIX B 233
- PROGRAMMING REFERENCE 233
- Programming Reference 234
- DSP56000 Family Manual 235
- Priority Interrupt 238
- (DSP56KFAMUM/AD) 240
- CENTRAL PROCESSOR 247
- PBC1 PBC0 251
- HTIEHCIE HRIEHF3 HF2 251
- DSP Side 251
- HTDEHCP HRDFHF1 HF0 252
- Processor Side 253
- Processor SideHI 254
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