Motorola VL-RISC MCF5202 User Manual

MOTOROLA GATEWAY BOARD 1 THE MOTOROLA GATEWAY BOARD (MCF5202 Microprocessor To MC68EC000 Bus Interface Card)Jeff MillerOctober 15, 1997 1.0 Introduct

10 GATEWAY BOARD MOTOROLA "pLSI property 'LOCK ISPMODE 30';pLSI property 'LOCK AD0 38';pLSI property 'LOCK MODE 40&apos

MOTOROLA GATEWAY BOARD 11 !BG68K pin 16 istype 'output'; "nBG68K!BGCF pin 20 istype 'output'; "nBGCFLDAT pin 22 istype

12 GATEWAY BOARD MOTOROLA ATMA.clk = TS; "ATM is latched when TS is assertedNQ1.ar = RSTI;NQ2.ar = RSTI;NQ1.clk= PCLK; "Clock NegClk machin

MOTOROLA GATEWAY BOARD 13 "Function Codes for EC000 - (See NOTE 1)" FC2 = ( (ATM & Normal-Access) # (IACK-Access) )FC2 = ( ATM # (TT1&a

14 GATEWAY BOARD MOTOROLA STATE BS1: "Got a Request, wait for CF to quit driving the busBGCF=0; BG68K=0; "Do not assert either Grant IF !BD

MOTOROLA GATEWAY BOARD 15 9.0 Block Diagram Figure 5: Gateway Board Block Diagram 10.0 Gateway Board Physical Layout Figure 6: Physical Layout (Act

16 GATEWAY BOARD MOTOROLA 11.0 Gateway Board Bill Of Material Table 5: Bill Of Material ITEM QTY MANUFACTURER PART NO. REF. DES. DESCRIPTION 1 1 Moto

MOTOROLA GATEWAY BOARD 17 12.0 ColdFire Gateway Board Schematics (1 of 2)CLK87CLKRSTnRST677473727170TCKTMS/BKPTTDI/DSITDO/DSOTRST/DSCLKDDATA0DDATA1DD

18 GATEWAY BOARD MOTOROLA ColdFire Gateway Board Schematics (2 of 2)D12D11D10D9D8D7D6D56162636465666768EC000 CONNJ1 / AGNDD4D3D2D1D0nASUDS12345678LDS

MOTOROLA GATEWAY BOARD 19Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty

2 GATEWAY BOARD MOTOROLA2.1.1 Mapping 32-bit MCF5202 addresses to 24-bit 68EC000 addresses The Gateway board transfers only the lower 24-bits of the

MOTOROLA GATEWAY BOARD 3 cache mode to cache-inhibit. This will require the microprocessor to go to external memory to get accurate data as opposed

4 GATEWAY BOARD MOTOROLA The industry standard Dhrystone 2.1 benchmark was run on the Motorola Gateway board, as well as some other systems, and the

MOTOROLA GATEWAY BOARD 5 Table 4: Dhrystone 2.1 Benchmark Performance 4.0 Potential Performance and System Improvements To fully take advantage of th

6 GATEWAY BOARD MOTOROLA 6.0 Bus Operation The Gateway board supports a synchronous interface between the MCF5202 bus and the MC68EC000 bus. The wav

MOTOROLA GATEWAY BOARD 7Figure 2: Longword Write To A 16-Bit PortCLOCKw S0S2S4S6 wPS1wPS1 PS2 PS3 PS4 PS5 PS1S0 S2 S4 S6 w wPS2 PS3 PS4 PS5 PS1 PS1w

8 GATEWAY BOARD MOTOROLAFigure 3: Interrupt-Acknowledge OperationCLOCKVECTOR011101 or01TS*R/W*TT[1:0]ATMSIZ[1:0]AD[23:5]DA*[1:0]FC[2:0]A[23:4]AS*UDS

MOTOROLA GATEWAY BOARD 9 7.0 PLD State Diagram Figure 4: SimpliÞed PLD State Diagram 8.0 PLD ABEL Code MODULE gatewayTITLE 'The controlling