Motorola MC9S12GC-Family manuals

Motorola MC9S12GC-Family User Manual (12 pages)

Brand: Motorola | Category: Networking | Size: 0.07 MB |

English

Table of contents

Chapter 1

1

1.1.2 Modes of Operation

2

1.2 Memory Map and Registers

3

1.2.2 Detailed Register Map

4

1.2.3 Part ID Assignments

5

Table 1-5. Signal Properties

6

1.3.5 Power Supply Pins

8

1.4 System Clock Description

9

1.5 Modes of Operation

9

1.5.3 Low-Power Modes

10

1.6.2 Resets

11

1.7.1 PPAGE

11

Rev 01.24

12

Motorola MC9S12GC-Family User Manual (136 pages)

Brand: Motorola | Category: Networking | Size: 1.96 MB |

English

Table of contents

MC9S12C Family

1

Device User Guide

1

Covers also

1

MC9S12GC Family

1

Revision History

2

Table of Contents

5

Section 4 Modes of Operation

6

List of Figures

11

List of Tables

13

MC9S12 C32 C FU 25

18

Terminology

22

Section 1 Introduction

23

1.3 Modes of Operation

25

1.4 Block Diagram

27

1.5 Device Memory Map

28

1.6 Detailed Register Map

33

00000000

38

Bit 15 14 13 12 11 10 9 Bit 8

38

Bit 7 654321Bit 0

38

$0070 - $007F Reserved

40

$00A0 - $00C7 Reserved

41

$00D0 - $00D7 Reserved

42

$0110 - $013F Reserved

45

$0180 - $023F Reserved

47

1.7 Part ID Assignments

50

Section 2 Signal Description

52

Bold italic

53

PP4/KWP4/PW4

53

PW3/KWP3/PP3

53

Table 2-1 Signal Properties

55

2.3.3 TEST / VPP — Test Pin

57

2.4 Power Supply Pins

63

Section 4 Modes of Operation

65

4.3 Security

66

4.4 Low Power Modes

67

5.1 Overview

68

5.2 Vectors

68

5.3 Resets

69

5.3.1 Reset Summary Table

70

5.3.2 Effects of Reset

70

6.1.1 PPAGE

70

6.1.2 BDM alternate clock

71

7.1.1 VREGEN

72

7.1.2 VDD1, VDD2, VSS1, VSS2

72

Component Purpose Type Value

73

Oscillator in

74

Colpitts mode

74

9.1.1 XCLKS

80

A.1 General

83

A.1.3 Pins

84

A.1.4 Current Injection

84

A.1.7 Operating Conditions

86

A.1.9 I/O Characteristics

89

A.1.10 Supply Currents

92

B.3 Output Loads

96

B.3.2 Capacitive Loads

97

B.4 ATD Characteristics

99

NOTE: Figure B-2

104

Table B-6

104

B.5 NVM, Flash and EEPROM

105

B.5.2 NVM Reliability

107

B.6.1 Startup

109

B.6.2 Oscillator

110

B.6.3 Phase Locked Loop

111

B.7 MSCAN

117

B.8 SPI

119

C.1 Master Mode

119

Min Typ Max

120

C.2 Slave Mode

121

C.3 External Bus Timing

123

D.1 General

127

D.2 80-pin QFP package

128

D.3 52-pin LQFP package

129

D.4 48-pin LQFP package

130

E.1 General

131

E.1.1 PK[2:0] / XADDR[16:14]

132

E.2 112-pin LQFP package

133

Device User Guide End Sheet

135

FINAL PAGE OF

136

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