Motorola M68EVB912B32 Service Manual

Order this document by MC68HC912B32TS/D M This document contains information on a new product. Specifications and information herein are subject to c

MOTOROLA MC68HC912B3210 MC68HC912B32TS/D3.2 Power Supply PinsMC68HC912B32 power and ground pins are described below and summarized in Table 4. 3.2.1

MOTOROLA MC68HC912B32100 MC68HC912B32TS/DIE — Interrupt EnableDetermines whether the BDLC will generate CPU interrupt requests in the run mode. It do

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 101RX4XE — Receive 4X EnableReception of a BREAK symbol automatically clears this bit and sets the BSVR registe

MOTOROLA MC68HC912B32102 MC68HC912B32TS/DFigure 25 Types of In-Frame ResponseTSIFR — Transmit Single Byte IFR with No CRC (Type 1 and Type 2)Used to

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 103Decreases the CPU overhead associated with servicing interrupts while operating a serial communica-tion prot

MOTOROLA MC68HC912B32104 MC68HC912B32TS/DUsed to pass data to be transmitted to the J1850 bus from the CPU to the BDLC. It is also used to passdata t

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 105The BDLC port DLC functions as a general-purpose I/O port. BDLC functions takes precedence overthe general-p

MOTOROLA MC68HC912B32106 MC68HC912B32TS/DRead and write anytime.DDDLC[6:0] — Data Direction Port DLC Pin 6 through Pin 00 = Configure I/O pin for inp

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 107If a BREAK symbol is received while the BDLC is transmitting or receiving, an invalid symbol interruptwill b

MOTOROLA MC68HC912B32108 MC68HC912B32TS/D15 Analog-To-Digital ConverterThe ATD is an 8-channel, 8-bit, multiplexed-input successive-approximation ana

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 109The ATD control register 2 and 3 are used to select the power up mode, interrupt control, and freezecontrol.

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 113.3 Signal Descriptions3.3.1 Crystal Driver and External Clock Input (XTAL, EXTAL)These pins provide the inte

MOTOROLA MC68HC912B32110 MC68HC912B32TS/DThe ATD control register 4 is used to select the clock source and set up the prescaler. Writes to the ATDcon

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 111The ATD control register 5 is used to select the conversion modes, the conversion channel(s), and ini-tiate

MOTOROLA MC68HC912B32112 MC68HC912B32TS/DTable 41 Multichannel Mode Result Register AssignmentS8CM CD CC CB CA Channel SignalResult in ADRxif MULT =

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 113The ATD status registers contain the flags indicating the completion of ATD conversions. Normally, it is rea

MOTOROLA MC68HC912B32114 MC68HC912B32TS/DRST — Module Reset BitWhen set, this bit causes all registers and activity in the module to assume the same

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 11516 Development SupportDevelopment support involves complex interactions between MC68HC912B32 resources and e

MOTOROLA MC68HC912B32116 MC68HC912B32TS/Dcommands, but can steal cycles from the CPU when necessary. Other BDM commands are firmwarebased, and requir

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 117Figure 27 BDM Host to Target Serial Bit TimingFigure 28 BDM Target to Host Serial Bit Timing (Logic 1)Figure

MOTOROLA MC68HC912B32118 MC68HC912B32TS/DFigure 29 BDM Target to Host Serial Bit Timing (Logic 0)Figure 29 shows the host receiving a logic zero from

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 119The CPU must be in background mode to execute commands that are implemented in the BDM ROM.The BDM ROM is lo

MOTOROLA MC68HC912B3212 MC68HC912B32TS/D3.3.3 Reset (RESET)An active low bidirectional control signal, RESET, acts as an input to initialize the MCU

MOTOROLA MC68HC912B32120 MC68HC912B32TS/D16.2.4 BDM RegistersSeven BDM registers are mapped into the standard 64-Kbyte address space when BDM is acti

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 121W/B — Word/Byte Transfer Flag0 = Byte transfer1 = Word transferBD/U — BDM Map/User Map FlagIndicates whether

MOTOROLA MC68HC912B32122 MC68HC912B32TS/DThis register can be read or written by BDM commands or firmware.ENBDM — Enable BDM (permit active backgroun

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 12316.3 BreakpointsHardware breakpoints are used to debug software on the MC68HC912B32 by comparing actual ad-d

MOTOROLA MC68HC912B32124 MC68HC912B32TS/D• Breakpoints are not allowed if the BDM mode is already active. Active mode means the CPU isexecuting out o

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 125This register is read/write in all modes.BKDBE — Enable Data BusEnables comparing of address or data bus val

MOTOROLA MC68HC912B32126 MC68HC912B32TS/DThese bits are used to compare against the most significant byte of the address bus.These bits are used to c

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 12716.4 Instruction TaggingThe instruction queue and cycle-by-cycle CPU activity can be reconstructed in real t

MC68HC912B32TS/DMHow to reach us:USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver Colorado 80217. 1-800-441-24

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 133.3.8 External Address and Data Buses (ADDR[15:0] and DATA[15:0])External bus pins share function with genera

MOTOROLA MC68HC912B3214 MC68HC912B32TS/DTable 5 MC68HC912B32 Signal Description SummaryPin Name Pin Number DescriptionPW[3:0] 3–6 Pulse Width Modulat

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 153.4 Port SignalsThe MC68HC912B32 incorporates eight ports which are used to control and access the various de

MOTOROLA MC68HC912B3216 MC68HC912B32TS/DWhen the PUPE bit in the PUCR register is set, PE[7,3,2,0] are pulled up. PE[7,3,2,0] are pulled up ac-tive d

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 17Register DDRT determines pin direction of port T when used for general-purpose I/O. When DDRT bitsare set, th

MOTOROLA MC68HC912B3218 MC68HC912B32TS/DTable 6 MC68HC912B32 Port Description SummaryPort NamePinNumbersData DirectionDD Register (Address) Descripti

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 193.5 Port Pull-Up, Pull-Down and Reduced DriveMCU ports can be configured for internal pull-up. To reduce powe

MOTOROLA MC68HC912B322 MC68HC912B32TS/D — Programmable Center-Aligned or Left-Aligned Outputs• Serial Interfaces— Asynchronous Serial Communications

MOTOROLA MC68HC912B3220 MC68HC912B32TS/D4 Register BlockThe register block can be mapped to any 2-Kbyte boundary within the standard 64-Kbyte address

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 21$0023 Bit 7 65432 1Bit 0 BRKAL$0024 Bit 15 14 13 12 11 10 9 Bit 8 BRKDH$0025 Bit 7 65432 1Bit 0 BRKDL$0026–$0

MOTOROLA MC68HC912B3222 MC68HC912B32TS/D$006F PAD7 PAD6 PAD5 PAD4 PAD3 PAD2 PAD1 PAD0 PORTAD$0070 Bit 7 65432 1Bit 0 ADR0H$0071 000000 0 0Reserved$00

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 23$0099 Bit 7 65432 1Bit 0 TC4 (L)$009A Bit 15 14 13 12 11 10 9 Bit 8 TC5 (H)$009B Bit 7 65432 1Bit 0 TC5 (L)$0

MOTOROLA MC68HC912B3224 MC68HC912B32TS/DNOTES:1. Port A, port B, and data direction registers DDRA and DDRB are not in map in expanded and peripheral

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 255 Operating Modes and Resource MappingEight possible operating modes determine the operating configuration of

MOTOROLA MC68HC912B3226 MC68HC912B32TS/DNormal Single-Chip Mode — There are no external address and data buses in this mode. All pins ofports A, B an

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 27MODE controls the MCU operating mode and various configuration options. This register is not in themap in per

MOTOROLA MC68HC912B3228 MC68HC912B32TS/DEME — Emulate Port ERemoving the registers from the map allows the user to emulate the function of these regi

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 29MMSWAI — Memory Mapping Interface Stop in Wait ControlThis bit controls access to the memory mapping interfac

Section Page MC68HC912B32 MOTOROLAMC68HC912B32TS/D 3 1 Introduction 1 1.1 Features ...

MOTOROLA MC68HC912B3230 MC68HC912B32TS/DThe 32-Kbyte Flash EEPROM can be mapped to either the upper or lower half of the 64-Kbyte addressspace. When

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 31ROMON — Enable Flash EEPROMIn expanded modes ROMON is reset to zero. In single-chip modes it is reset to one.

MOTOROLA MC68HC912B3232 MC68HC912B32TS/D6 Bus Control and Input/OutputInternally the MC68HC912B32 has full 16-bit data paths, but depending upon the

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 33Bits PA[7:0] are associated with addresses ADDR[15:8] and DATA[15:8]. When this port is not used forexternal

MOTOROLA MC68HC912B3234 MC68HC912B32TS/DThis register is associated with external bus control signals and interrupt inputs including data bus en-able

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 35In special single-chip mode, the E clock is enabled as a timing reference and the other bits of port E arecon

MOTOROLA MC68HC912B3236 MC68HC912B32TS/DThese bits select pull-up resistors for any pin in the corresponding port that is currently configured asan i

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 377 Flash EEPROMThe 32-Kbyte Flash EEPROM module for the MC68HC912B32 serves as electrically erasable and pro-g

MOTOROLA MC68HC912B3238 MC68HC912B32TS/DThis register controls the operation of the Flash EEPROM array. BOOTP cannot be changed when theLOCK control

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 39STRE — Spare Test Row EnableThe spare test row consists of one Flash EEPROM array row. The reserved word at l

Section Page TABLE OF CONTENTS (Continued) MOTOROLA MC68HC912B324 MC68HC912B32TS/D 11 Pulse-Width Modulator 63 11.1 PWM Register Description ...

MOTOROLA MC68HC912B3240 MC68HC912B32TS/DENPE — Enable Programming/Erase0 = Disables program/erase voltage to Flash EEPROM1 = Applies program/erase vo

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 41the longest possible life expectancy. This method requires stopping the program/erase sequence at pe-riods of

MOTOROLA MC68HC912B3242 MC68HC912B32TS/D7.6 Programming the Flash EEPROMProgramming the Flash EEPROM is accomplished by the following sequence. The V

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 43 Figure 7 Program Sequence FlowSTART PROGSET LAT CLEAR ERAS WRITE DATATO ADDRESSSET ENPEREADGET NEXTADDRESS/D

MOTOROLA MC68HC912B3244 MC68HC912B32TS/D7.7 Erasing the Flash EEPROMThe following sequence demonstrates the recommended procedure for erasing the Fla

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 45 Figure 8 Erase Sequence FlowSTART ERASESET LAT SET ERAS WRITE TO ARRAYSET ENPEREADNOARRAY FAILED TO ERASEARR

MOTOROLA MC68HC912B3246 MC68HC912B32TS/D7.8 Program/Erase Protection InterlocksThe Flash EEPROM program and erase mechanisms provide maximum protecti

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 478 EEPROMThe MC68HC912B32 EEPROM serves as a 768-byte nonvolatile memory which can be used for fre-quently acc

MOTOROLA MC68HC912B3248 MC68HC912B32TS/DFigure 9 EEPROM Block Protect Mapping8.2 EEPROM Control RegistersEESWAI — EEPROM Stops in Wait Mode0 = Module

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 49BPROT[4:0] — EEPROM Block Protection0 = Associated EEPROM block can be programmed and erased.1 = Associated E

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 5 1.3 MC68HC912B32 Block DiagramFigure 1 MC68HC912B32 Block DiagramIOC0IOC1IOC2IOC3IOC4IOC5IOC6PAIOC7DDRTPORT

MOTOROLA MC68HC912B3250 MC68HC912B32TS/DBULKP — Bulk Erase Protection0 = EEPROM can be bulk erased.1 = EEPROM is protected from being bulk or row era

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 51A program or erase operation should follow the sequence below: 1. Write BYTE, ROW and ERASE to the desired v

MOTOROLA MC68HC912B3252 MC68HC912B32TS/D9 Resets and InterruptsCPU12 exceptions include resets and interrupts. Each exception has an associated 16-bi

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 539.3 Interrupt Control and Priority RegistersIRQE — IRQ Select Edge Sensitive Only0 = IRQ configured for low-l

MOTOROLA MC68HC912B3254 MC68HC912B32TS/DWrite only if I mask in CCR = 1 (interrupts inhibited). Read anytime.To give a maskable interrupt source high

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 559.5.2 Clock and Watchdog Control LogicThe COP watchdog system is enabled, with the CR[2:0] bits set for the s

MOTOROLA MC68HC912B3256 MC68HC912B32TS/DAfter the CCR is stacked, the I bit (and the X bit, if an XIRQ interrupt service request is pending) is setto

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 5710 Clock FunctionsClock generation circuitry generates the internal and external E-clock signals as well as i

MOTOROLA MC68HC912B3258 MC68HC912B32TS/D10.5 Clock Function RegistersAll register addresses shown reflect the reset state. Registers may be mapped to

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 59RTIF — Real-Time Interrupt FlagThis bit is cleared automatically by a write to this register with this bit se

MOTOROLA MC68HC912B326 MC68HC912B32TS/D 2 Central Processing Unit The CPU12 is a high-speed, 16-bit processing unit. It has full 16-bit data paths a

MOTOROLA MC68HC912B3260 MC68HC912B32TS/DAlways reads $00. Writing $55 to this address is the first step of the COP watchdog sequence.Writing $AA to t

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 61Figure 12 Clock Chain for SCI, BDLC, RTI, COPPCLKSC0BDMODULUS DIVIDER:÷ 1, 2, 3, 4, 5, 6, ..., 8190, 8191SCI0

MOTOROLA MC68HC912B3262 MC68HC912B32TS/DFigure 13 Clock Chain for TIMFigure 14 Clock Chain for SPI, ATD and BDMBITS: PR2, PR1, PR0PCLK1:0:01:0:11:1:0

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 6311 Pulse-Width ModulatorThe pulse-width modulator (PWM) subsystem provides four independent 8-bit PWM wavefor

MOTOROLA MC68HC912B3264 MC68HC912B32TS/DFigure 16 Block Diagram of PWM Center-Aligned Output ChannelGATEPWCNTx8-BIT COMPARE =PWDTYx8-BIT COMPARE =PWP

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 65Figure 17 PWM Clock Sources11.1 PWM Register DescriptionRead and write anytime.CON23 — Concatenate PWM Channe

MOTOROLA MC68HC912B3266 MC68HC912B32TS/DCON01 — Concatenate PWM Channels 0 and 1When concatenated, channel 0 becomes the high-order byte and channel

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 67PPOL3 — PWM Channel 3 Polarity0 = Channel 3 output is low at the beginning of the clock cycle; high when the

MOTOROLA MC68HC912B3268 MC68HC912B32TS/DPWPRES is a free-running 7-bit counter. Read anytime. Write only in special mode (SMOD = 1).Read and write an

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 69Read and write anytime. A write will cause the PWM counter to reset to $00. In special mode, if DISCR = 1, a

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 7 2.2 Data Types The CPU12 supports the following data types:• Bit data• 8-bit and 16-bit signed and unsigned

MOTOROLA MC68HC912B3270 MC68HC912B32TS/DRead and write anytime.The value in each duty register determines the duty of the associated PWM channel. Whe

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 71PSBCK — PWM Stops while in Background Mode0 = Allows PWM to continue while in background mode.1 = Disable PWM

MOTOROLA MC68HC912B3272 MC68HC912B32TS/D11.2 PWM Boundary CasesThe boundary conditions for the PWM channel duty registers and the PWM channel period

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 7312 Standard Timer ModuleThe standard timer module consists of a 16-bit software-programmable counter driven b

MOTOROLA MC68HC912B3274 MC68HC912B32TS/D12.1 Timer RegistersInput/output pins default to general-purpose I/O lines until an internal function which u

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 75When the OC7Mn bit is set, a successful OC7 action will override a successful OC[6:0] compare actionduring th

MOTOROLA MC68HC912B3276 MC68HC912B32TS/DRead or write anytime.OMn — Output ModeOLn — Output Level These eight pairs of control bits are encoded to sp

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 77The bits in TMSK1 correspond bit-for-bit with the bits in the TFLG1 status register. If cleared, the cor-resp

MOTOROLA MC68HC912B3278 MC68HC912B32TS/DThe newly selected prescale factor will not take effect until the next synchronized edge where all pres-cale

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 79Depending on the TIOS bit for the corresponding channel, these registers are used to latch the valueof the fr

MOTOROLA MC68HC912B328 MC68HC912B32TS/D2.4 Indexed Addressing ModesThe CPU12 indexed modes reduce execution time and eliminate code size penalties fo

MOTOROLA MC68HC912B3280 MC68HC912B32TS/DPEDGE — Pulse Accumulator Edge Control For PAMOD = 0 (event counter mode)0 = Falling edges on the pulse accum

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 81Full count register access should take place in one clock cycle. A separate read/write for high byte andlow b

MOTOROLA MC68HC912B3282 MC68HC912B32TS/DRead or write anytime.0 = Configures the corresponding I/O pin for input only 1 = Configures the correspondin

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 8313 Serial InterfaceThe serial interface of the MC68HC912B32 consists of two independent serial I/O sub-system

MOTOROLA MC68HC912B3284 MC68HC912B32TS/DFigure 20 Serial Communications Interface Block Diagram13.2.1 Data FormatThe serial data format requires the

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 8513.2.2 SCI Baud Rate GenerationThe basis of the SCI baud rate generator is a 13-bit modulus counter. This cou

MOTOROLA MC68HC912B3286 MC68HC912B32TS/DBTST — Baud Register TestReserved for test functionBSPL — Baud Rate Counter SplitReserved for test function B

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 87WAKE — Wakeup by Address Mark/Idle 0 = Wake up by IDLE line recognition 1 = Wake up by address mark (last dat

MOTOROLA MC68HC912B3288 MC68HC912B32TS/DRWU — Receiver Wake-Up Control0 = Normal SCI Receiver1 = Enables the wake-up function and inhibits further re

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 89NF — Noise Error FlagSet during the same cycle as the RDRF bit but not set in the case of an overrun (OR).0 =

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 93 Pinout and Signal Descriptions3.1 MC68HC912B32 Pin AssignmentsThe MC68HC912B32 is available in a 80-pin quad

MOTOROLA MC68HC912B3290 MC68HC912B32TS/DR7/T7–R0/T0 — Receive/Transmit Data Bits 7 to 0Reads access the eight bits of the read-only SCI receive data

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 91 Figure 21 Serial Peripheral Interface Block DiagramA clock phase control bit (CPHA) and a clock polarity con

MOTOROLA MC68HC912B3292 MC68HC912B32TS/DFigure 22 SPI Clock Format 0 (CPHA = 0)Figure 23 SPI Clock Format 1 (CPHA = 1)tLBegin EndSCK (CPOL=0)SAMPLE I

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 9313.3.3 SS OutputAvailable in master mode only, SS output is enabled with the SSOE bit in the SP0CR1 register

MOTOROLA MC68HC912B3294 MC68HC912B32TS/DRead or write anytime.SPIE — SPI Interrupt Enable1 = Hardware interrupt sequence is requested each time the S

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 95Read anytime. Write anytime.At reset, E Clock divided by 2 is selected.SPR[2:0] — SPI Clock (SCK) Rate Select

MOTOROLA MC68HC912B3296 MC68HC912B32TS/D(read or write) to the SP0DR register.0 = No write collision1 = Indicates that a serial transfer was in progr

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 97DDS0 — Data Direction for Port S Bit 2 and Bit 0If the SCI receiver is configured for two-wire SCI operation,

MOTOROLA MC68HC912B3298 MC68HC912B32TS/D14 Byte Data Link Communications Module (BDLC)The byte data link communications module (BDLC) provides access

MC68HC912B32 MOTOROLAMC68HC912B32TS/D 9914.3 Loopback ModesTwo loopback modes are used to determine the source of bus faults.Digital Loopback is used